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| DATASHEET VALUE-LINE TWO-CHANNEL AC'97 CODECS OVERVIEW Value-Line Stereo AC'97 CODECs with headphone drive and SPDIF outputs. STAC9750/9751 DESCRIPTION IDT's STAC9750/9751 are general purpose, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component Specification Rev. 2.2). They have 18-bit ADCs and 20-bit DACs. The STAC9750/9751 incorporate IDT's proprietary technology to achieve a DAC SNR in excess of 89dB. The DACs, ADCs and mixer are integrated with analog I/ Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. The STAC9750/9751 include digital input/output capability for support of modern PC systems and also an output that supports the SPDIF format. The STAC9750/9751 is a standard 2-channel stereo CODEC. With IDT's headphone drive capability, headphones can be driven with no external amplifier. The STAC9750/9751 may be used as a secondary CODEC, with the STAC9700/21/44/56/08/84/66 as the primary, in a multiple CODEC configuration conforming to the AC'97 Rev. 2.2 specification. This configuration can provide the true six-channel, AC-3 playback required for DVD applications. The STAC9750/9751 communicates via the five-wire AC-Link to any digital component of AC'97, providing flexibility in the audio system design. The STAC9750/9751 supports General Purpose Input/Output (GPIO), as well as SPDIF output. These digital I/O options provide for a number of advanced architectural implementations, with volume controls and digital mixing capabilities built directly into the CODEC. Packaged in an AC'97 compliant 48-pin TQFP, the STAC9750/9751 can be placed on the motherboard, daughter boards, PCI, AMR, CNR, or ACR cards. FEATURES * * * * * * * * * * * * * * * * Full Duplex Stereo 18-bit ADCs and 20-bit DACs AC'97 Rev 2.2 Compliant High Performance Technology SPDIF Output Crystal Elimination Circuit Headphone amplifier Independent Sample Rates for ADCs & DACs (hardware SRCs) 20dB or 30dB Microphone Boost Capability 90dB SNR LINE-LINE 5-Wire AC-Link Protocol Compliance Digital-Ready Architecture General Purpose I/O +3.3 V (STAC9751) and +5 V (STAC9750) Analog Power Supply Options Pin Compatible With STAC9700/21/56/66 IDT Surround (SS3D) Stereo Enhancement Energy Saving Dynamic Power Modes KEY SPECIFICATIONS * * * * * * Analog LINE_OUT SNR: 90dB Digital DAC SNR: 89dB Digital ADC SNR: 85dB Full-scale Total Harmonic Distortion: 0.005% Crosstalk between Input Channels: -70dB Spurious Tone Rejection: 100dB RELATED MATERIALS * * * Data Sheet Reference Designs for MB, CNR, ACR and PCI applications Audio Precision Performance Plots IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 1 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO TABLE OF CONTENTS 1. PRODUCT BRIEF ...................................................................................................................... 5 1.1. Features ............................................................................................................................................ 5 1.2. Description ........................................................................................................................................ 5 1.3. STAC9750/9751 Block Diagram ........................................................................................................ 6 1.4. Key Specifications ............................................................................................................................. 7 1.5. Related Materials .............................................................................................................................. 7 1.6. Additional Support ............................................................................................................................. 7 2. CHARACTERISTICS/SPECIFICATIONS .................................................................................. 8 2.1. Electrical Specifications ..................................................................................................................... 8 2.2. AC Timing Characteristics ............................................................................................................... 15 3. TYPICAL CONNECTION DIAGRAM ....................................................................................... 19 4. AC-LINK ................................................................................................................................... 20 4.1. Clocking ........................................................................................................................................... 20 4.2. Reset ............................................................................................................................................... 20 5. DIGITAL INTERFACE .............................................................................................................. 21 5.1. AC-Link Digital Serial Interface Protocol ......................................................................................... 21 5.2. AC-Link Low Power Mode ............................................................................................................... 29 5.3. Waking up the AC-Link .................................................................................................................... 30 6. STAC9750/9751 MIXER .......................................................................................................... 31 6.1. Analog Mixer Input .......................................................................................................................... 33 6.2. Analog Mixer Output ........................................................................................................................ 33 6.3. SPDIF Digital Mux ........................................................................................................................... 33 6.4. PC Beep Implementation ................................................................................................................ 33 6.5. Programming Registers ................................................................................................................... 34 7. LOW POWER MODES ............................................................................................................56 8. MULTIPLE CODEC SUPPORT ...............................................................................................58 8.1. Primary/Secondary CODEC Selection ............................................................................................ 58 8.2. Secondary CODEC Register Access Definitions ............................................................................. 59 9. TESTABILITY .......................................................................................................................... 60 10. PIN DESCRIPTION ................................................................................................................ 61 10.1. Digital I/O ....................................................................................................................................... 62 10.2. Analog I/O ..................................................................................................................................... 63 10.3. Filter/References/GPIO ................................................................................................................. 64 10.4. Power and Ground Signals ........................................................................................................... 64 11. ORDERING INFORMATION .................................................................................................. 65 12. PACKAGE DRAWINGS ......................................................................................................... 66 12.1. 48-Pin LQFP .................................................................................................................................. 66 13. SOLDER REFLOW PROFILE ...............................................................................................67 13.1. Standard Reflow Profile Data ........................................................................................................ 67 13.2. Pb Free Process - Package Classification Reflow Temperatures ................................................. 68 14. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION .............................. 69 15. APPENDIX B: PROGRAMMING REGISTERS .....................................................................71 16. REVISION HISTORY ............................................................................................................. 72 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 2 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO LIST OF FIGURES Figure 1. STAC9750/9751 Block Diagram ...................................................................................................... 6 Figure 2. Cold Reset Timing ......................................................................................................................... 15 Figure 3. Warm Reset Timing ....................................................................................................................... 15 Figure 4. Clocks Timing ................................................................................................................................ 16 Figure 5. Data Setup and Hold Timing ......................................................................................................... 17 Figure 6. Signal Rise and Fall Times Timing ................................................................................................ 17 Figure 7. AC-Link Low Power Mode Timing ................................................................................................. 18 Figure 8. ATE Test Mode Timing .................................................................................................................. 18 Figure 9. STAC9751 Typical Connection Diagram ....................................................................................... 19 Figure 10. AC-Link to its Companion Controller ........................................................................................... 20 Figure 11. AC'97 Standard Bi-directional Audio Frame ................................................................................ 22 Figure 12. AC-Link Audio Output Frame ...................................................................................................... 22 Figure 13. Start of an Audio Output Frame ................................................................................................... 23 Figure 14. STAC9750/9751 Audio Input Frame ........................................................................................... 26 Figure 15. Start of an Audio Input Frame ..................................................................................................... 26 Figure 16. STAC9750/9751 Powerdown Timing ......................................................................................... 29 Figure 17. STAC9750 2-Channel Mixer Functional Diagram .................................................................. 31 Figure 18. STAC9751 2-Channel Mixer Functional Diagram ....................................................................... 32 Figure 19. Example of STAC9750/9751 Powerdown/Powerup Flow ........................................................... 56 Figure 20. STAC9750/9751 Powerdown/Powerup Flow With Analog Still Active ........................................ 57 Figure 21. STAC9750/9751 Pin Description Drawing ................................................................................... 61 Figure 22. Package Drawing - 48-pin LQFP .................................................................................................. 66 Figure 23. Reflow Profile .............................................................................................................................. 67 Figure 24. STAC9750/9751 Split Independent Power Supply Operation Typical Connection Diagram ....... 70 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 3 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO LIST OF TABLES Table 1. STAC9751 Analog Performance Characteristics ............................................................................. 13 Table 2. Cold Reset Specifications ................................................................................................................ 15 Table 3. Warm Reset Specifications .............................................................................................................. 15 Table 4. Clocks Specifications ....................................................................................................................... 16 Table 5. Clock Mode Configuration ............................................................................................................... 16 Table 6. Data Setup and Hold Specifications ................................................................................................ 17 Table 7. Signal Rise and Fall Times Specifications ....................................................................................... 17 Table 8. AC-Link Low Power Mode Timing Specifications ............................................................................ 18 Table 9. ATE Test Mode Specifications ......................................................................................................... 18 Table 10. STAC9750/9751 Available Data Streams ...................................................................................... 21 Table 11. Command Address Port Bit Assignments ...................................................................................... 23 Table 12. Command Data Port Bit Assignments ........................................................................................... 24 Table 13. Status Address Port Bit Assignments ............................................................................................ 27 Table 14. Status Data Port Bit Assignments .................................................................................................. 27 Table 15. Programming Registers ................................................................................................................. 34 Table 16. Play Master Volume Register ........................................................................................................ 35 Table 17. PC_BEEP Register ........................................................................................................................ 36 Table 18. Analog Mixer Input Gain Register .................................................................................................. 37 Table 19. Record Select Control Registers ................................................................................................... 39 Table 20. Record Gain Registers ................................................................................................................. 39 Table 21. General Purpose Register ............................................................................................................. 40 Table 22. 3D Control Registers .................................................................................................................... 40 Table 23. Powerdown Status Registers ......................................................................................................... 42 Table 24. Extended Audio ID ......................................................................................................................... 43 Table 25. Slot assignment relationship between SPSA1 and SPSA0 ........................................................... 45 Table 26. STAC9750/9751 AMAP compliant ................................................................................................. 45 Table 27. Hardware Supported Sample Rates .............................................................................................. 45 Table 28. SPDIF Control ............................................................................................................................... 46 Table 29. Extended Moden Status and Control ............................................................................................. 47 Table 31. GPIO Pin Polarity/Type Register ................................................................................................... 48 Table 32. GPIO Pin Sticky Register ............................................................................................................... 48 Table 30. GPIO Pin Configuration Register ................................................................................................... 48 Table 33. GPIO Pin Mask Register ................................................................................................................ 49 Table 35. Digital Audio Control Register ........................................................................................................ 50 Table 34. GPIO Pin Status Register .............................................................................................................. 50 Table 36. ADC data on AC LINK ................................................................................................................... 52 Table 37. Mic Boost Select ............................................................................................................................ 52 Table 38. Analog Current Adjust ................................................................................................................... 53 Table 39. GPIO Access Registers (74h) ........................................................................................................ 54 Table 40. Low Power Modes ......................................................................................................................... 56 Table 41. CODEC ID Selection ..................................................................................................................... 58 Table 42. Secondary CODEC Register Access Slot 0 Bit Definitions ........................................................... 59 Table 43. Digital Connection Signals ............................................................................................................. 62 Table 44. Analog Connection Signals ........................................................................................................... 63 Table 45. Filtering and Voltage References .................................................................................................. 64 Table 46. Power and Ground Signals ............................................................................................................ 64 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 4 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 1. PRODUCT BRIEF 1.1. Features * * * * * * * * * * * * * * * * Full duplex stereo 18-bit ADC and 20-bit DAC AC'97 Rev 2.2-compliant High performance technology SPDIF output Crystal elimination circuit Headphone amplifier Independent sample rates for ADCs & DACs (hardware SRCs) 20dB or 30dB microphone boost capability 90dB SNR LINE-LINE 5-Wire AC-Link protocol compliance Digital-Ready architecture General Purpose I/O +3.3 V (STAC9751) and +5 V (STAC9750) analog power supply options Pin compatible with the STAC9700/21/44/08/56/66/52 IDT Surround (SS3D) Stereo Enhancement Energy saving dynamic power modes 1.2. Description IDT's STAC9750/9751 are general purpose 18-bit ADC, 20-bit DAC, full duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio Codec `97 Component Specification Rev. 2.2). The STAC9750/9751 incorporate IDT's proprietary technology to achieve a DAC SNR in excess of 90 dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. The STAC9750/9751 include digital input/output capability for support of modern PC systems with an output that supports the SPDIF format. The STAC9750/9751 is a standard 2-channel stereo CODEC. With IDT's headphone drive capability, headphones can be driven with no external amplifier. The STAC9750/9751 may be used as a secondary CODEC, with the STAC9700/21/44/ 56/08/84/66 as the primary, in a multiple CODEC configuration conforming to the AC'97 Rev. 2.2 specification. This configuration can provide the true six-channel, AC-3 playback required for DVD applications. The STAC9750/9751 communicates via the five-wire AC-Link to any digital component of AC'97, providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin LQFP, the STAC9750/9751 can be placed on a motherboard, daughter boards, PCI, AMR, CNR, or ACR cards. The STAC9750/9751 block diagram is illustrated in Figure 1. It provides variable sample rate Digital-to-Analog (DA) and Analog-to-Digital (AD) conversion, mixing, and analog processing. Supported audio sample rates include 48 KHz, 44.1 KHz, 32 KHz, 22.05 KHz, 16 KHz, 11.025 KHz, and 8 KHz; additional rates are supported in the STAC9750/9751 soft audio drivers. The digital interface communicates with the AC'97 controller via the five-wire AC-Link and contains the 64-word by 16-bit reg- IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 5 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO isters. The two DACs convert the digital stereo PCM-out content to audio. The MIXER block combines the PCM_OUT with any analog sources, to drive the LINE_OUT and HP_OUT outputs. The MONO_OUT delivers either microphone only, or a mono mix of sources from the MIXER. The stereo variable sample rate ADCs provide record capability for any mix of mono or stereo sources, and deliver a digital stereo PCM_IN signal back to the AC-Link. The microphone input and mono input can be recorded simultaneously, thus allowing for an all digital output in support of the digital ready initiative. All ADCs operate at 18-bit resolution and DACs at 20-bit resolution. For a digital ready record path, the microphone is connected to the left channel ADC while the mono output of the stereo mixer is connected to right channel ADC. Make sure the microphone input is not connected to the stereo mixer when in this mode. The STAC9750/9751 supports General Purpose Input/Output (GPIO), as well as SPDIF output. These digital I/O options provide for a number of advanced architectural implementations, with volume controls and digital mixing capabilities built directly into the CODEC. The STAC9750/9751 is designed primarily to support stereo (2-speaker) audio. True AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-CODEC option available in the STAC9750/9751 to support multiple CODECs in an AC'97 architecture. Additionally, the STAC9750/9751 provides for a stereo enhancement feature, IDT Surround 3D (SS3D). SS3D provides the listener with several options for improved speaker separation beyond the normal 2/ 4-speaker arrangements. Together with the logic component (controller or advanced core logic chip-set) of AC'97, STAC9750/ 9751 can be SoundBlaster(R) and Windows Sound System(R) compatible with IDT's WDM driver for WIN 98/2K/ME/XP. SoundBlaster is a registered trademark of Creative Labs. Windows is a registered trademark of Microsoft Corporation. 1.3. STAC9750/9751 Block Diagram Figure 1. STAC9750/9751 Block Diagram Power Management 4 stereo sources 2 mono sources Stereo Mono HP_OUT PCM out DACs AC-link SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# DAC Digital Interface Registers 64x16 bits DAC MIXER ADC ADC PCM in ADCs Analog mixing and Gain Control LINE_OUT MONO_OUT Multi-Codec CID0 CID1 Mic Boost 0,20 or 30 dB M MIC1 U X MIC2 Variable Sample Rate 20-Bit DACs and 18-Bit ADCs SPDIF IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 6 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 1.4. Key Specifications * * * * * * Analog LINE_OUT SNR: 90 dB Digital DAC SNR: 89 dB Digital ADC SNR: 85 dB Full-scale Total Harmonic Distortion: 0.005% Crosstalk between Input Channels: -70 dB Spurious Tone Rejection: 100 dB 1.5. Related Materials * * * Product Brief Reference Designs for MB, AMR, CNR, and ACR applications Audio Precision Performance Plots 1.6. Additional Support Additional product and company information can be obtained by going to the IDT website at: www.IDT.com IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 7 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2. CHARACTERISTICS/SPECIFICATIONS 2.1. Electrical Specifications Absolute Maximum Ratings: 2.1.1. Stresses above the ratings listed below can cause permanent damage to the STAC9750/9751. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Maximum supply voltage Output current per pin Voltage on any pin relative to ground Operating temperature Storage temperature Soldering temperature Pin Vdd 5.5 Volts Maximum Rating 4 mA, except VREF_OUT = 5mA Vss - 0.3 V to Vdd + 0.3 V 0oC to +70oC -55 oC to +125 oC 260 oC for 10 seconds * Soldering temperature information for all available packages begins on page 67. 2.1.2. Recommended Operation Conditions Parameter Min. Digital - 3.3 V Analog - 5 V Analog - 3.3 V 3.135 4.75 3.135 0 Tcase (48-LQFP) Typ. 3.3 5 3.3 Max. 3.465 5.25 3.465 +70 +90 Units V V V C C Power Supply Voltage Ambient Operating Temperature Case Temperature ESD: The STAC9750/9751 is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the STAC9750/9751 implements internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or performance. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 8 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.1.3. Power Consumption Parameter Digital Supply Current + 3.3 V Digital Analog Supply Current (at Reset state) + 5 V Analog + 3.3 V Analog Power Down Status (individually asserted) All PR measurements taken while unmuted. +5 V Analog Supply Current All paths unmuted +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR0 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR1 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR2 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR3 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR4 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR5 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR6 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR0 & PR1 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR0, PR1, PR2, PR6 +3.3 V Analog Supply Current +3.3 V Digital Supply Current +5 V Analog Supply Current PR0, PR1, PR2, PR3, PR6 +3.3 V Analog Supply Current +3.3 V Digital Supply Current Min - Typ 30 35 35 Max - Unit mA mA mA - - - - - - - - - - - 50 44 33 42 39 22 41 38 28 32 29 12 23 19 12 50 44 0.2 50 44 12 38 36 33 35 35 12 5 5 12 0.6 0.6 12 - mA - mA - mA - mA - mA - mA - mA - mA - mA - mA - mA IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 9 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.1.4. Revision Comparison CA3 Analog 5V No PR PR0 PR1 PR2 PR3 PR4 PR5 PR6 78 62 63 48 40 76 75 97 CC1 Digital 3.3 V 27 23 24 27 21 1 7.5 27 % Of Savings Digital 3.3 V 33 22 28 12 12 0.2 12 33 Analog 5V 50 42 41 32 23 50 50 38 Analog 5V 36% 32% 35% 33% 43% 34% 33% 61% Digital 3.3 V -22% 4% -17% 56% 43% 80% -60% -22% 3.3 V 69 56 52 42 35 68 68 61 3.3 V 44 39 38 29 19 44 44 36 3.3 V 36% 30% 27% 31% 46% 35% 35% 41% PR bit individually asserted. All PR measurements taken while unmuted. 2.1.5. AC-Link Static Digital Specifications (Tambient = 25 C, DVdd = 3.3 V 5%, AVss=DVss=0 V; 50 pF external load) Parameter Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (AC-Link outputs - Hi-Z) Output buffer drive current Symbol Vin Vil Vih Voh Vol - Min -0.30 0.65xDVdd 0.90xDVdd -10 -10 - Typ 4 Max DVdd + 0.30 0.35xDVdd 0.1xDVdd 10 10 - Unit V V V V V A A mA IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 10 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.1.6. STAC9750 Analog Performance Characteristics (Tambient = 25 C, AVdd = 5.0 V 5%, DVdd = 3.3 V 5%, AVss=DVss=0 V; 1 KHz input sine wave; Sample Frequency = 48 KHz; 0dB = 1 Vrms, 10 K / 50 pF load, Testbench Characterization BW: 20 Hz - 20 KHz, 0dB settings on all gain stages) Parameter Min 20 84 74 20 19,200 28,800 100 55 70 100 100 1.5 50 15 0.5 X AVdd Typ 1.0 0.03 1.0 1.0 1.0 50 90 90 89 85 89 89 89 80 - Max 20,000 19,200 28,800 1 - Unit Vrms Vrms Vrms Vrms Vrms mW dB dB dB dB Hz dB dB dB dB dB Hz Hz Hz dB dB ms dB dB dB dB K pF V Full Scale Input Voltage: All Analog Inputs except Microphone Microphone Inputs (Note 1) Full Scale Output: Line Output PCM (DAC) to LINE_OUT MONO_OUT HEADPHONE_OUT (32 load) (peak) Analog S/N: (Note 2) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT LINE_IN to A/D with High pass filter enabled Analog Frequency Response (Note 3) Total Harmonic Distortion: (Note 4) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT (full scale) LINE_IN to A/D with High pass filter enabled HEADPHONE_OUT A/D & D/A Digital Filter Pass Band (Note 5) A/D & D/A Digital Filter Transition Band A/D & D/A Digital Filter Stop Band A/D & D/A Digital Filter Stop Band Rejection (Note 6) DAC Out-of-Band Rejection (Note 7) Group Delay (48KHz sample rate) Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency) Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency) Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance (Note 8) Input Capacitance VREF_OUT IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 11 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Parameter Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Min - Typ - Max 0.5 0.5 Unit dB dB Note: 1. 2. 3. 4. 5. 6. 7. 8. With +30 dB Boost on, 1.0 Vrms with Boost off. Ratio of Full Scale signal to idle channel noise output is measured "A weighted" over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 1dB limits for Line Output & 0 dB gain. Ratio of Full Scale signal to THD+N output with -3dB signal, measured "A weighted" over a 20 KHz BW, 48 KHz Sample Frequency. 0.25dB limits Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. For all inputs except PC BEEP. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 12 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.1.7. STAC9751 Analog Performance Characteristics (Tambient = 25 C, AVdd = DVdd = 3.3 V 5%, AVss=DVss=0 V; 1 KHz input sine wave; Sample Frequency = 48 KHz; 0dB = 1 Vrms, 10 K / 50 pF load, Testbench Characterization BW: 20 Hz - 20 KHz, 0dB settings on all gain stages) Parameter Min 20 74 20 19,200 28,800 100 55 - Typ 1.0 0.03 0.5 0.5 0.5 12.5 90 90 89 85 89 89 89 84 80 70 100 100 1.5 50 15 0.5 X AVdd Max 20,000 19,200 28,800 1 - Unit Vrms Vrms Vrms Vrms Vrms mW dB dB dB dB Hz dB dB dB dB dB Hz Hz Hz dB dB ms dB dB dB dB K pF V Full Scale Input Voltage: All Analog Inputs except Microphone Microphone Inputs (Note 1) Full Scale Output: Line Output PCM (DAC) to LINE_OUT MONO_OUT HEADPHONE_OUT (32 load) (peak) Analog S/N: (Note 2) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT LINE_IN to A/D with High pass filter enabled Analog Frequency Response (Note 3) Total Harmonic Distortion: (Note 4) CD to LINE_OUT Other to LINE_OUT D/A to LINE_OUT (full scale) LINE_IN to A/D with High pass filter enabled HEADPHONE_OUT A/D & D/A Digital Filter Pass Band (Note 5) A/D & D/A Digital Filter Transition Band A/D & D/A Digital Filter Stop Band A/D & D/A Digital Filter Stop Band Rejection (Note 6) DAC Out-of-Band Rejection (Note 7) Group Delay (48 KHz sample rate) Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency) Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency) Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance (Note 8) Input Capacitance VREF_OUT Table 1. STAC9751 Analog Performance Characteristics IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 13 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Parameter Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift Min - Typ 100 Max 0.5 0.5 - Unit dB dB ppm/C Table 1. STAC9751 Analog Performance Characteristics (Continued) Note: 1. 2. With +30 dB Boost on, 1.0 Vrms with Boost off. Ratio of Full Scale signal to idle channel noise output is measured "A weighted" over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).0 dB gain, 20 KHz BW, 48 KHz Sample Frequency 1 dB limits. 1dB limits for Line Output & 0 dB gain. Ratio of Full Scale signal to THD+N output with -3dB signal, measured "A weighted" over a 20 KHz BW, 48 KHz Sample Frequency. 0.25dB limits Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. For all inputs except PC BEEP. 3. 4. 5. 6. 7. 8. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 14 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.2. AC Timing Characteristics (Tambient = 25 C, AVdd = 3.3 V or 5 V 5%, DVdd = 3.3 V 5%, AVss = DVss = 0 V; 50 pF external load) 2.2.1. Cold Reset Figure 2. Cold Reset Timing Trst2clk Tres_low RESET# BIT_CLK SDATA_IN Table 2. Cold Reset Specifications Parameter RESET# active low pulse width RESET# inactive to BIT_CLK startup delay Symbol Tres_low Trst2clk Min 1.0 162.8 Typ - Max - Units s ns Note: BIT_CLK and SDATAIN are in a high impedance state during reset. 2.2.2. Warm Reset Figure 3. Warm Reset Timing Tsync_high Tsync_2clk SYNC BIT_CLK Table 3. Warm Reset Specifications Parameter SYNC active high pulse width SYNC inactive to BIT_CLK startup delay Symbol Tsync_high Tsync2clk Min 1.0 162.8 Typ 1.3 - Max - Units s ns IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 15 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.2.3. Clocks Figure 4. Clocks Timing Tclk_low BIT_CLK Tclk_high Tclk_period Tsync_low Tsync_high SYNC Tclk_period Table 4. Clocks Specifications Parameter BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulse width (Note 1) BIT_CLK low pulse width (Note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Note: 1. Worst case duty cycle restricted to 45/55. Tsync_period Tsync_high Tsync_low Tclk_high Tclk_low Tclk_period Symbol Min 36 36 - Typ 12.288 81.4 750 40.7 40.7 48.0 20.8 1.3 19.5 Max 45 45 - Units MHz ns ps ns ns KHz s s s The STAC9750/9751 supports several clock frequency inputs as described in the following table. In general, when a 24.576 MHz clock XTAL is not used, the XTAL_OUT pin should be tied to ground. This short to ground configures the part into an alternate clock mode and enables an on board PLL. Table 5. Clock Mode Configuration XTL_OUT Pin Config XTAL XTAL or open XTAL or open XTAL or open short to ground short to ground short to ground short to ground CID1 Pin Config float float pulldown pulldown float float pulldown pulldown CID0 Pin Config float pulldown float pulldown float pulldown float pulldown Clock Source Input 24.576 MHz XTAL 12.288 MHz BIT_CLK 12.288 MHz BIT_CLK 12.288 MHz BIT_CLK 14.31818 MHz source 27 MHz source 48 MHz source 24.576 MHz source CODEC Mode P S S S P P P P CODEC ID 0 1 2 3 0 0 0 0 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 16 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.2.4. Data Setup and Hold (47.5-75 pF external load) Figure 5. Data Setup and Hold Timing tc o B IT _ C L K SD ATA_O U T S D A T A _ IN SYNC V ih V oh V ol T s e tu p V il T h o ld Table 6. Data Setup and Hold Specifications Parameter Setup to falling edge of BIT_CLK Symbol Tsetup Min 10 Typ - Max - Units ns ns Hold from falling edge of BIT_CLK Thold 10 Note: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller. 2.2.5. Signal Rise and Fall Times (75pF external load; from 10% to 90% of Vdd) Figure 6. Signal Rise and Fall Times Timing B IT _ C L K T r is e c lk T f a llc lk S D A T A _ IN T r is e d in T f a lld in Table 7. Signal Rise and Fall Times Specifications Parameter BIT_CLK rise time BIT_CLK fall time SDATA_IN rise time SDATA_IN fall time Symbol Triseclk Tfallclk Trisedin Tfalldin Min - Typ - Max 6 6 6 6 Units ns ns ns ns IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 17 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 2.2.6. AC-Link Low Power Mode Timing Figure 7. AC-Link Low Power Mode Timing SYNC B IT _ C L K SDATA_O UT S D A T A _ IN N o te : B IT _ C L K n o t to s c a le W r ite to 0x20 D a ta P R 4 D o n 't c a r e Ts2_pdow n S lo t 1 S lo t 2 Table 8. AC-Link Low Power Mode Timing Specifications Parameter End of Slot 2 to BIT_CLK, SDATA_IN low Symbol Ts2_pdown Min - Typ - Max 1.0 Units s 2.2.7. ATE Test Mode Figure 8. ATE Test Mode Timing RESET# SDATA_O U T T s e tu p 2 r s t S D A T A _ IN , B IT _ C L K T o ff H i- Z Table 9. ATE Test Mode Specifications Parameter Setup to trailing edge of RESET# (also applies to SYNC) Rising edge of RESET# to Hi-Z delay Symbol Tsetup2rst Toff Min 15.0 - Typ - Max 25.0 Units ns ns Note: 1. 2. 3. All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge of RESET# causes the STAC9750/9751 AC-Link outputs to go high-impedance, which is suitable for ATE in-circuit testing. Once the test mode has been entered, the STAC9750/9751 must be issued another RESET# with all AC-Link signals low to return to the normal operating mode. # denotes active low. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 18 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 3. TYPICAL CONNECTION DIAGRAM Figure 9. STAC9751 Typical Connection Diagram 2 * Ferrite Bead* *Suggested 3.3V 5% 0.1 F 1 F 0.1 F 0.1 F 10 F 0.1 F 25 AVdd1 38 AVdd2 1 DVdd1 9 27 pF DVdd2 XTL_IN 2 24.576 MHz 12 PC_BEEP 13 PHONE SDATA_OUT 14 AUX_L 15 AUX_R 16 VIDEO_L RESET# 17 VIDEO_R 18 CD_L 19 CD_GND 20 CD_R VREF 21 MIC1 22 MIC2 23 LINE_IN_L 24 LINE_IN_R *OPTIONAL 32 0.1 F 1 F* GPIO0 LINE_OUT_L 820 pF 29 AFILT1 LINE_OUT_R MONO_OUT AFILT2 HP_OUT_L AVss1 26 AVss2 42 DVss1 4 DVss2 7 HP_OUT_R 39 41 CAP2 GPIO1 HP_COMM NC NC NC SPDIF 31 33 34 48 40 44 43 35 36 37 VREFOUT 28 27 CID0 45 46 47 SDATA_IN SYNC BIT_CLK 5 6 8 10 11 XTL_OUT 3 27 pF 22 EMI Filter 27 pF *OPTIONAL STAC9751 CID1 EAPD *OPTIONAL 0.1 F 1 F* 820 pF 30 *Terminate ground plane as close to codec as possible Analog Ground Digital Ground Note: 1. 2. 3. 4. See Appendix A for specific connection requirements prior to operation. See Figure 24 on page 70 for split supply connections. Pin 48: To Enable SPDIF, use an 1 KW-10 KW external pulldown. To Disable SPDIF, use an 1 KW-10 KW external pullup. Do NOT leave Pin 48 floating. The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 19 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 4. AC-LINK Figure 10 shows the AC-Link point to point serial interconnect between the STAC9750/9751 and its companion controller. All digital audio streams and command/status information are communicated over this AC-Link. See "Digital Interface" on page 21 for details. Figure 10. AC-Link to its Companion Controller S YN C BIT _C LK XT A L_IN A D igital D C '97 C ontroller SD AT A _O U T SD AT A _IN R ES E T# A C '97 C odec XT A L_O U T 4.1. Clocking STAC9750/9751 derives its clock internally from an externally connected 24.576 MHz crystal or an oscillator, through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the BIT_CLK pin at 12.288 MHz. The beginning of all audio sample packets, or "Audio Frames", transferred over AC-Link is synchronized to the rising edge of the "SYNC" signal driven by the AC'97 controller. Data is transitioned on AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving side on each immediately following falling edge of BIT_CLK. 4.2. Reset There are 3 types of resets: 1. a "cold" reset where all STAC9750/9751 logic and registers are initialized to their default state 2. a "warm" reset where the contents of the STAC9750/9751 register set are left unaltered 3. a "register" reset which only initializes the STAC9750/9751 registers to their default states After signaling a reset to the STAC9750/9751, the AC'97 controller should not attempt to play or capture audio data until it has sampled a "CODEC Ready" indication via register 26h from the STAC9750/9751. For proper reset operation SDATA_OUT should be 0 during cold reset. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 20 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 5. DIGITAL INTERFACE 5.1. AC-Link Digital Serial Interface Protocol The STAC9750/9751 communicates to the AC'97 controller via a 5-wire, digital, serial, AC-Link interface, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands and status information are communicated over this point-to-point serial interconnect. The AC-Link handles multiple input and output audio streams, as well as control register accesses using a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data transaction. Table 10 shows the data streams available on the STAC9750/9751: Table 10. STAC9750/9751 Available Data Streams PCM Playback PCM Record data Control Status 2 output slots 2 input slots 2 output slots 2 input slots 2 Channel composite PCM output stream 2 Channel composite PCM input stream Control register write port Control register read port Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The STAC9750/ 9751 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support twelve 20-bit outgoing and incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-Link data, STAC9750/9751 for outgoing data and AC'97 controller for incoming data, samples each serial bit on the falling edges of BIT_CLK. The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 Reserved trailing bit positions) time slot (Slot 0) wherein each bit conveys a "slot-valid" tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the data, (STAC9750/9751 for the input stream, AC'97 controller for the output stream), to stuff all bit positions with 0s during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Additionally, for power savings, all clock, SYNC, and data signals can be halted by the controller. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 21 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Figure 11. AC'97 Standard Bi-directional Audio Frame SYNC OUTGOING STREAMS INCOMING STREAMS TAG PHASE TAG CMD ADR CMD DATA PCM LEFT PCM RT NA PCM CTR PCM LSURR PCM RSURR PCM LFE PCM LALT PCM RALT RSVD TAG STATUS ADR STATUS DATA PCM LEFT PCM RT NA NA RSVD RSVD RSVD RSVD RSVD RSVD DATA PHASE 5.1.1. AC-Link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the STAC9750/9751 DAC inputs, and control registers. Each audio output frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special Reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by the STAC9750/9751 indicate which of the corresponding 12 times slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-Link at its fixed 48 KHz audio frame rate. The following diagram illustrates the time slot based AC-Link protocol. Figure 12. AC-Link Audio Output Frame Data Phase Tag Phase 20.8 uS (48 kHZ) SYNC BIT_CLK SDATA_OUT 12.288 MHz valid Frame slot1 slot2 slot(12) "0" CID1 CID0 19 "0" 19 "0" 19 "0" 19 "0" End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9750/9751 samples the assertion of SYNC. This following edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9750/ 9751 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams, are time aligned. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 22 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Figure 13. Start of an Audio Output Frame SYNC a s s e rte d f ir s t SDATA_O UT b it o f f r a m e SYNC B IT _ C L K SDATA_O U T E n d o f p r e v io u s a u d io f r a m e v a lid F ra m e s lo t 1 s lo t 2 SDATA_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions stuffed with 0s by the AC'97 controller. When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data. 5.1.1.1. Slot 1: Command Address Port The command port is used to control features and monitor status (see Audio Input Frame Slots 1 and 2) of the STAC9750/9751 functions including, but not limited to, mixer settings and power management (refer to the Control Register section of this specification). The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Odd accesses are considered invalid and return 0000h. Audio output frame slot 1 communicates control register address and write/read command information to the STAC9750/9751. Table 11. Command Address Port Bit Assignments Bit 19 18:12 11:0 Description Read/Write command Control Register Index Reserved 1= read, 0=write Comments Sixty-four 16-bit locations, addressed on even byte boundaries Stuffed with 0s The first bit (MSB) sampled by STAC9750/9751 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are Reserved and must be stuffed with 0s by the AC'97 controller. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 23 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 5.1.1.2. Slot 2: Command Data Port The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by Slot 1, bit 19). Table 12. Command Data Port Bit Assignments Bit 19:4 3:0 Description Control Register Write Data Reserved Stuffed with 0s Comments Stuffed with 0s if current operation is a read If the current command port operation is a read cycle, then the entire slot time must be stuffed with 0s by the AC'97 controller. 5.1.1.3. Slot 3: PCM Playback Left Channel Audio output frame slot 3 is the composite digital audio left playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. 5.1.1.4. Slot 4: PCM Playback Right Channel Audio output frame slot 4 is the composite digital audio right playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. 5.1.1.5. Slot 5: Reserved Audio output frame slot 5 is Reserved for modem operation and is not used by the STAC9750/9751. 5.1.1.6. Slot 6: PCM Center Channel Audio output frame slot 6 is the composite digital audio center stream used in a multi-channel application where the STAC9750/9751 is programmed to accept the primary DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi-channel programming options. 5.1.1.7. Slot 7: PCM Left Surround Channel Audio output frame slot 7 is the composite digital audio left surround stream. In the default state, the STAC9750/9751 accepts PCM data from slots 7 and 8 for the surround DACs, for output to the DAC_OUT pins. As a programming option, PCM data from slots 7 and 8 may be used to supply data to the primary DACs when slots 6 and 9 are used to drive the surround DACs. Please refer to the register programming section for details on the multi-channel programming options. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 24 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 5.1.1.8. Slot 8: PCM Right Surround Channel Audio output frame slot 8 is the composite digital audio right surround stream. As a programming option, PCM data from slots 7 and 8 may be used to supply data to the primary DACs. Please refer to the register programming section for details on the multi-channel programming options. 5.1.1.9. Slot 9: PCM Low Frequency Channel Audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel application where the STAC9750/9751 is programmed to accept the primary DAC PCM data from slots 6 and 9. Please refer to the register programming section for details on the multi-channel programming options. 5.1.1.10. Slot 10: PCM Alternate Left Audio output frame slot 10 is the composite digital audio alternate left stream used in a multi-channel applications. Please refer to the register programming section for details on the multi channel programming options. 5.1.1.11. Slot 11: PCM Alternate Right Audio output frame slot 11 is the composite digital audio alternate right stream used in a multi-channel applications. Please refer to the register programming section for details on the multi channel programming options. 5.1.1.12. Slot 12: Reserved Audio output frame slot 12 is Reserved for modem operations and is not used by the STAC9750/ 9751. 5.1.2. AC-Link Audio Input Frame (SDATA_IN) The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC'97 controller. As is the case for audio output frame, each AC-Link audio input frame consists of twelve 20-bit time slots. Slot 0 is a special Reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9750/ 9751 is in the "CODEC Ready" state or not. If the "CODEC Ready" bit is a 0, this indicates that STAC9750/9751 is not ready for normal operation. This condition is normal following the de-assertion of power on reset, for example, while STAC9750/9751's voltage references settle. When the AC-Link "CODEC Ready" indicator bit is a 1, it indicates that the AC-Link and STAC9750/9751 control/status registers are in a fully operational state. The AC'97 controller must further probe the Powerdown Control Status Register (refer to Mixer Register section) to determine exactly which subsections, if any, are ready. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 25 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Prior to any attempts at putting STAC9750/9751 into operation the AC'97 controller should poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9750/9751 has become "CODEC Ready". Once the STAC9750/9751 is sampled "CODEC Ready", the next 12 bit positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. The following diagram illustrates the time slot based AC-Link protocol. Figure 14. STAC9750/9751 Audio Input Frame Data Phase Tag Phase 20.8 uS (48 kHZ) SYNC BIT_CLK SDATA_IN 12.288 MHz valid Frame slot1 slot2 slot(12) "0" "0" "0" 19 "0" 19 "0" 19 "0" 19 "0" End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. Immediately following the falling edge of BIT_CLK, the STAC9750/9751 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9750/9751 transitions SDATA_IN into the first bit position of slot 0 ("CODEC Ready" bit). Each new bit position is presented to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. Figure 15. Start of an Audio Input Frame SYNC a s s e rte d f ir s t SD ATA _O U T b it o f f r a m e SYNC B IT _ C L K S D A T A _ IN E n d o f p r e v io u s a u d io f r a m e C od ec R eady s lo t 1 s lo t 2 SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by STAC9750/9751. SDATA_IN data is sampled on the falling edges of BIT_CLK. 5.1.2.1. Slot 1: Status Address Port The status port is used to monitor status for STAC9750/9751 functions including, but not limited to, mixer settings and power management. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 26 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Audio input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged "valid" by STAC9750/ 9751 during slot 0.) Table 13. Status Address Port Bit Assignments Bit 19 18:12 11:2 1:0 Reserved Control Register Index Slot Request Reserved Description Stuffed with 0 Comments Echo of register index for which data is being returned see sections below Stuffed with 0 The first bit (MSB) generated by STAC9750/9751 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0 by the STAC9750/9751. 5.1.2.2. Slot 2: Status Data Port The status data port delivers 16-bit control register read data. Table 14. Status Data Port Bit Assignments Bit 19:4 3:0 Reserved Description Control Register Read Data Stuffed with 0 Comments Stuffed with 0 if tagged "invalid" If Slot 2 is tagged "invalid" by STAC9750/9751, then the entire slot will be stuffed with 0's. 5.1.2.3. Slot 3: PCM Record Left Channel Audio input frame slot 3 is the left channel output of STAC9750/9751 input MUX, post-ADC. STAC9750/9751 ADCs are implemented to support 18-bit resolution. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. 5.1.2.4. Slot 4: PCM Record Right Channel Audio input frame slot 4 is the right channel output of STAC9750/9751 input MUX, post-ADC. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. 5.1.2.5. Slot 5: Reserved Audio input frame slot 5 is Reserved for modem operation and is not used by the STAC9750/9751. This slot is always stuffed with 0. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 27 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 5.1.2.6. Slot 6: PCM Left Record Channel Audio input frame slot 6 is the left channel output of STAC9750/9751 input MUX, post-ADC. STAC9750/9751 ADCs are implemented to support 18-bit resolution. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. See section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.7. Slot 7: PCM Left Record Channel Audio input frame slot 7 is the left channel output of STAC9750/9751 input MUX, post-ADC. STAC9750/9751 ADCs are implemented to support 18-bit resolution. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. See section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.8. Slot 8: PCM Right Record Channel Audio input frame slot 8 is the right channel output of STAC9750/9751 input MUX, post-ADC. STAC9750/9751 ADCs are implemented to support 18-bit resolution. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. See section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.9. Slot 9: PCM Right Record Channel Audio input frame slot 9 is the right channel output of STAC9750/9751 input MUX, post-ADC. STAC9750/9751 ADCs are implemented to support 18-bit resolution. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. See section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.10. Slot 10: PCM Left Record Channel Audio input frame slot 10 is the left channel output of STAC9750/9751 input MUX, post-ADC. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 28 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO STAC9750/9751 ADCs are implemented to support 18-bit resolution. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. See section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.11. Slot 11: PCM Right Record Channel Audio input frame slot 11 is the right channel output of STAC9750/9751 input MUX, post-ADC. STAC9750/9751 ADCs are implemented to support 18-bit resolution. STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. See section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.12. Slot 12: Reserved Audio input frame slot 12 is Reserved for modem operation and is not used by the STAC9750/9751. This slot is always stuffed with 0. 5.2. AC-Link Low Power Mode The STAC9750/9751 AC-Link can be placed in the low power mode by programming register 26h to the appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage level. The AC'97 controller can wake up the STAC9750/9751 by providing the appropriate reset signals. Figure 16. STAC9750/9751 Powerdown Timing SYNC BIT_CLK SDATA_OUT SDATA_IN Note: BIT_CLK not to scale slot 2 per fram e TAG W rite to 0x20 DATA PR4 slot 2 per fram e TAG BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 controller driver is at the point where it is ready to program the AC-Link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 29 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the STAC9750/9751 to this low power mode. 5.3. Waking up the AC-Link Once the STAC9750/9751 has halted BIT_CLK, there are only two ways to "wake up" the AC-Link. Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a "Cold AC'97 Reset", and a "Warm AC'97 Reset". The current power down state would ultimately dictate which form of reset is appropriate. Unless a "cold" or "register" reset (a write to the Reset register) is performed, wherein the AC'97 registers are initialized to their default values, registers are required to keep state during all power down modes. Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. When AC-Link powers up it indicates readiness via the CODEC Ready bit (input slot 0, bit 15). Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time, and then bringing RESET# back HIGH. The reset occurs on the rising edge when RESET# is deasserted. By asserting and deasserting RESET#, BIT_CLK and SDATA_IN will be activated, or re-activated as the case may be, and all STAC9750/9751 control registers will be initialized to their default power-on-reset values. Note: RESET# is an asynchronous input. (# denotes active low) Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9750/9751 register values. A warm reset is signaled by driving SYNC high for a minimum of 1 s in the absence of BIT_CLK. Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9750/ 9751. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 30 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6. STAC9750/9751 MIXER The STAC9750/9751 includes analog and digital mixers for maximum flexibility. The analog mixer is designed to the AC'97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. The analog mixer also includes several extensions of the AC'97 specification to support "all analog record" capability as well as "POP BYPASS" mode for all digital playback. The analog sources include: * * * * * * System Audio: digital PCM input and output for business, games and multimedia CD/DVD: analog CD/DVD-ROM audio with internal connections to CODEC mixer Mono microphone: choice of desktop microphone, with programmable boost and gain Speakerphone: use of system microphone and speakers for telephone, DSVD, and video conferencing Video: TV tuner or video capture card with internal connections to CODEC mixer AUX/synth: analog FM or wavetable synthesizer, or other internal source The digital mixer includes inputs for the PCM DAC and the recorded ADC output Figure 17. STAC9750 2-Channel Mixer Functional Diagram KEY MonoAnalog 2Ah:D5-D4 28h: D5-D4 Slot Select 6Ah:D1 StereoAnalog PCM to SPDIF SPDIF Digital MUX PCMOut Slot Select 18h DAC PC_BEEP Phone 20h:D8 0Eh:D6 vol 0Ah 0Ch mute vol vol vol vol vol vol vol mute mute MUX mute mute mute mute mute AllAnalog vs AllRecord -6dB 04h Headphone Volume 02h 3D HP_OUT Analog Audio Sources MIC1 MIC2 LINEIN CD AUX VIDEO 20 or 30 dB 6E:D2 0Eh 10h 12h 16h 14h 20h:D15 -6dB Master Volume 06h 3D LINE_OUT MUX 6Eh:D12 1Ah MUX 20h:D9 Mono Volume 1Ch MONO_OUT MUX 3D Record Volume ADC Slot Select PCMIn ADCRecord Ganged3DControl 20h:D13 22h:D2-D3 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 31 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Source PC_BEEP PHONE MIC1 MIC2 LINE_IN CD VIDEO AUX PCM out MONO input Desktop microphone Second microphone External audio source Audio from CD-ROM Function PC BEEP pass through to LINE_OUT Connection From PC_BEEP output From telephony subsystem From microphone jack From second microphone jack From line-in jack Cable from CD-ROM Cable from TV or VidCap card Internal connector AC-Link Audio from TV tuner or video camera Upgrade synth or other external source Digital audio output from AC'97 Controller Destination HP_OUT LINE_OUT MONO_OUT PCM in SPDIF Function Stereo mix of all sources Stereo mix of all sources Microphone or MONO Analog mixer output Digital data from the CODEC to the AC'97 Controller SPDIF digital audio output Connection To headphone out jack To output jack To telephony subsystem AC-Link To SPDIF output connector Figure 18. STAC9751 2-Channel Mixer Functional Diagram KEY MonoAnalog 2Ah:D5-D4 Slot Select 28h: D5-D4 StereoAnalog 6Ah:D1 PCMOut Slot Select PCM to SPDIF SPDIF Digital MUX 18h DAC PC_BEEP Phone 20h:D8 0Eh:D6 vol -6dB 0Ah 0Ch mute vol vol vol vol vol vol vol mute mute MUX mute mute mute mute mute AllAnalog vs AllRecord -6dB 04h Headphone Volume 02h 3D HP_OUT Analog Audio Sources MIC1 MIC2 20 or -6dB 30 dB 6E:D2 0Eh 10h 12h 20h:D15 -6dB Master Volume 06h 3D LINE_OUT LINEIN CD -6dB MUX 6Eh:D12 1Ah MUX AUX VIDEO -6dB -6dB -6dB -6dB 16h 14h Mono Volume MONO_OUT 20h:D9 1Ch MUX 3D Record Volume +6dB ADC Slot Select PCMIn ADCRecord Ganged3DControl 20h:D13 22h:D2-D3 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 32 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.1. Analog Mixer Input The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9750/9751 supports the following input sources: * * * Any mono or stereo source Mono or stereo mix of all sources Two-channel input with mono output reference (microphone + stereo mix) Note: All unused inputs should be tied together connected to ground through a capacitor (0.1 F suggested). 6.2. Analog Mixer Output The mixer generates three distinct outputs: * * * A stereo mix of all sources for output to the LINE_OUT and HP_OUT A stereo mix of all analog sources for recording Microphone only or mono mix of all sources for MONO_OUT Note: Mono output of stereo mix is attenuated by -6 dB. 6.3. SPDIF Digital Mux The STAC9750/9751 incorporates a digital output that supports SPDIF formats. A multiplexer determines which of two digital input streams are used for the digital output conversion process. These two streams include the PCM OUT data from the audio controller and the ADC recorded output. The normal analog LINE_OUT signal can be converted to the SPDIF formats by using the internal ADC to record the "MIX" output, which is the combination of all analog and all digital sources. In the case of digital controllers with support for 4 or more channels, the SPDIF output mode can be used to support compressed 6-channel output streams for delivery to home theater systems. These can be routed on alternate AC-Link slots to the SPDIF output, while the standard 2-channel output is delivered as selected by bits D5 and D4 in Register 6E. If the digital controller supports 6 channels, a SPDIF output with 4 analog channels can also be configured (in a multi-CODEC setup). For more information for SPDIF please see 6.5.12.2; page 44. Pin 48: To Enable SPDIF, use an 1 K-10 K external pulldown. To Disable SPDIF, use an 1 K-10 K external pullup. Do NOT leave Pin 48 floating. 6.4. PC Beep Implementation PC Beep is active on power up and defaults to an un-muted state. The PC_BEEP input is routed directly to the MONO_OUT, LINE_OUT and HP_OUT pins of the CODEC. Because the PC_BEEP input drive is often a full scale digital signal, some resistive attenuation of the PC_BEEP input is recommended to keep the beep tone within reasonable volume levels. The user should mute this input before using any other mixer input because the PC Beep input can contribute noise to the lineout during normal operation. This style of PC Beep is related to the AC'97 Specification Rev 2.2. To use the analog PC Beep, a value of 00h to bits F[7:0](D[12:5]) disables the Digital PC Beep generation. PV[3:0] (D[4:1]) controls the volume level from 0 to 45dB of attenuation in 3dB steps. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 33 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5. Programming Registers Table 15. Programming Registers Address 00h 02h 04h 06h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 24h 26h 28h 2Ah 2Ch 32h 3Ah 3Eh 4Ch 4Eh 50h 52h 54h 6Ah 6Ch 6Eh 70h 72h 74h* 76h 78h 7Ch 7Eh Name Reset Master Volume HP_OUT Mixer Volume Master Volume MONO PC Beep Mixer Volume Phone Mixer Volume Microphone Mixer Volume Line In Mixer Volume CD Mixer Volume Video Mixer Volume Aux Mixer Volume PCM Out Mixer Volume Record Select Record Gain General Purpose 3D Control Audio Interrupt Powerdown Control/Status Extended Audio ID Extended Audio Control/Status PCM DAC Rate PCM LR ADC Rate SPDIF Control Extended Modem Control/Status GPIO Pin Configuration GPIO Pin Polarity/Type GPIO Pin Sticky GPIO Wake-up GPIO Pin Status Digital Audio Control Revision Code Analog Special 72h Enable Analog Current Adjust GPIO Current Access 78h Enable Clock Access Vendor ID1 Vendor ID2 Default 6990h 8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h 000Fh 0205h 0400h BB80h BB80h 2A00h 0100h 0003h FFFFh 0000h 0000h 0000h 0000h 00xxh 0000h 0000h 0000h 0000h 0000h 0000h 8384h 76xxh Location 6.5.1; page 35 6.5.2.1; page 35 6.5.2.2; page 35 and 35 6.5.2.3; page 36 6.5.3; page 36 6.5.4.1; page 37 6.5.4.2; page 37 6.5.4.3; page 37 6.5.4.4; page 38 6.5.4.5; page 38 6.5.4.6; page 38 6.5.4.7; page 38 6.5.5; page 38 6.5.6; page 39 6.5.7; page 39 6.5.8; page 40 6.5.9; page 41 6.5.10; page 41 6.5.11; page 42 6.5.12; page 44 6.5.14; page 46 6.5.15; page 46 6.5.16; page 46 6.5.17; page 47 6.5.18; page 47 6.5.19; page 48 6.5.20; page 48 6.5.21; page 49 6.5.22; page 49 6.5.16; page 46 6.5.24; page 51 6.5.25; page 51 6.5.25.6; page 53 6.5.25.7; page 53 6.5.26; page 54 6.5.27.1; page 54 6.5.27.2; page 55 6.5.28.1; page 55 6.5.28.2; page 55 * Register 74h is used for GPIO control in revision CA3. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 34 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.1. Reset (00h) Default: 6990h D15 RSRVD4 D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns the ID code of the part. 6.5.2. Play Master Volume Registers (Index 02h, 04h, and 06h) These registers manage the output signal volumes. Register 02h controls the stereo LINE_OUT master volume (both right and left channels), register 04h controls the Headphone Out master volume, and register 06h controls the MONO volume output. Each step corresponds to 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. ML5 through ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5 through MM0 is for the mono out channel. When bits D5 and D13 are set in any of these registers it automatically writes all 1 to the next lower 5-bits. The default value is 8000h for registers 02h, 04h, and 06h, which corresponds to 0 dB attenuation with mute on. Table 16. Play Master Volume Register Mute 0 0 1 Mx5...Mx0 00 0000 01 1111 xx xxxx Function 0dB Attenuation 46.5 Attenuation dB Attenuation Range Req. Req. Req. 6.5.2.1. Master Volume (02h) Default: 8000h Note: If optional bits D13 & D5 of register 02h are set to 1, then the corresponding attenuation is set to 46.5dB and the register reads will produce 1Fh as a value for this attenuation/gain block. D15 Mute D14 RSRVD D13 ML5 D12 ML4 D11 ML3 D10 ML2 D9 ML1 D8 ML0 D7 Reserved D6 D5 MR5 D4 MR4 D3 MR3 D2 MR2 D1 MR1 D0 MR0 6.5.2.2. Headphone Out Volume (04h) Default: 8000h IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 35 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Note: If optional bits D13 & D5 of register 04h are set to 1, then the corresponding attenuation is set to 46.5dB and the register reads will produce 1Fh as a value for this attenuation/gain block. D15 Mute D14 RSRVD D13 HPL5 D12 HPL4 D11 HPL3 D10 HPL2 D9 HPL1 D8 HPL0 D7 Reserved D6 D5 HPR5 D4 HPR4 D3 HPR3 D2 HPR2 D1 HPR1 D0 HPR0 6.5.2.3. Master Volume MONO (06h) Default: 8000h Note: If optional bit D5 of register 06h is set to 1, then the corresponding attenuation is set to 46.5dB and the register reads will produce 1Fh as a value for this attenuation/gain block. D15 Mute D14 D6 Reserved D13 D5 MM5 D12 D4 MM4 D11 Reserved D10 D2 MM2 D9 D1 MM1 D8 D0 MM0 D7 D3 MM3 6.5.3. PC Beep Mixer Volume (Index 0Ah) Default: 0000h Note: PC_BEEP defaults to 0000h, mute off. D15 Mute D14 D6 Reserved D13 D5 D12 D4 PV3 D11 Reserved D10 D2 PV1 D9 D1 PV0 D8 D0 RSRVD D7 D3 PV2 This register controls the level for the PC Beep input. Each step corresponds to approximately 3dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel is set at -dB. PC_BEEP supports motherboard implementations. The intention of routing PC_BEEP through the STAC9750/9751 mixer is to eliminate the requirement for an onboard speaker by guaranteeing a connection to speakers connected via the output jack. In order for this to be viable, the PC_BEEP signal needs to reach the output jack at all times. NOTE: the PC_BEEP is routed to the mono outputs when the STAC9750/9751 is in a RESET state. This is so that Power On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. For further PC_BEEP implementation details please refer to the AC'97 Technical FAQ sheet. The default value is 0000h, which corresponds to 0 dB attenuation with mute off. Table 17. PC_BEEP Register Mute 0 0 1 PV3...PV0 0000 1111 xxxx Function 0 dB Attenuation 45 dB Attenuation dB Attenuation IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 36 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.4. Analog Mixer Input Gain Registers (Index 0Ch - 18h) These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to approximately 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. The default value for stereo registers is 8808h, corresponding to 0 dB gain with mute on. Table 18. Analog Mixer Input Gain Register Mute 0 0 0 Gx4...Gx0 0 0000 0 1000 1 1111 Function +12 dB gain 0 dB gain -34.5 dB gain 6.5.4.1. Phone Mixer Volume (0Ch) Default: 8008h D15 Mute D14 D6 Reserved D13 D5 D12 D4 GN4 D11 Reserved D10 D2 GN2 D9 D1 GN1 D8 D0 GN0 D7 D3 GN3 6.5.4.2. Mic Mixer Volume (0Eh) Default: 8008h D15 Mute D14 D6 BOOST_EN D13 D5 RSRVD D12 D4 GN4 D11 Reserved D10 D2 GN2 D9 D1 GN1 D8 D0 GN0 D7 RSRVD D3 GN3 Register 0Eh (Mic Volume Register) Bit D6 is the Mic boost enable. To select between 20dB or 30dB Mic Boost, see register 6Eh, D2 in section 6.5.25; page 51. 6.5.4.3. Line In Mixer Volume (10h) Default: 8808h D15 Mute D14 Reserved D13 D5 D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 D6 Reserved D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 37 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.4.4. CD Mixer Volume (12h) Default: 8808h D15 Mute D14 Reserved D13 D5 D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 D6 Reserved D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 6.5.4.5. Video Mixer Volume (14h) Default: 8808h D15 Mute D14 Reserved D13 D5 D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 D6 Reserved D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 6.5.4.6. AUX Mixer Volume (16h) Default: 8808h D15 Mute D14 Reserved D13 D5 D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 D6 Reserved D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 6.5.4.7. PCM Out Mixer Volume (18h) Default: 8808h D15 Mute D14 Reserved D13 D5 D12 GL4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 D6 Reserved D4 GR4 D3 GR3 D2 GR2 D1 GR1 D0 GR0 6.5.5. Record Select (1Ah) Default: 0000h (corresponding to Mic in) D15 D7 D14 D6 D13 Reserved D12 D4 D11 D3 D10 SL2 D9 SL1 D8 SL0 D5 Reserved D2 SR2 D1 SR1 D0 SR0 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 38 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Used to select the record source independently for right and left. Table 19. Record Select Control Registers Bit(s) 15:11 Reset 0 Name Reserved Left Channel Input Select Description Bits not used, should read back 0 000 = Mic 001 = CD In (left) 010 = Video In (left) 011 = Aux In (left) Right Channel Input Select 100 = Line In (left) 101 = Stereo Mix (left) 110 = Mono Mix 111 = Phone 10:8 0 SL2:SL0 7:3 0 Reserved Bits not used, should read back 0 000 = Mic 001 = CD In (right) 010 = Video In (right) 011 = Aux In (right) 100 = Line In (right) 101 = Stereo Mix (right) 110 = Mono Mix 111 = Phone 2:0 0 SR2:SR0 6.5.6. Record Gain (1Ch) Default: 8000h (corresponding to 0 dB gain with mute on) D15 Mute D14 D6 Reserved D13 Reserved D12 D4 D11 GL3 D10 GL2 D9 GL1 D8 GL0 D7 D5 D3 GR3 D2 GR2 D1 GR1 D0 GR0 The 1Ch register adjusts the stereo input record gain. Each step corresponds to 1.5dB. 22.5dB corresponds to 0F0Fh. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel(s) is set at -dB. Table 20. Record Gain Registers Mute 0 0 1 Gx3... Gx0 1111 0000 xxxx +22.5 dB gain 0 dB gain - gain Function 6.5.7. General Purpose (20h) Default: 0000h D15 POP BYP D14 RSRVD D13 3D D12 D4 D11 Reserved D10 D2 D9 MIX D8 MS D7 LPBK D6 D5 D3 Reserved D1 D0 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 39 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO This register is used to control some miscellaneous functions. Below is a summary of each bit and its function. The MS bit controls the MIC selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-Link, allowing for full system performance measurements. Table 21. General Purpose Register Bit 3D MIX MS POP BYP LPBK Function 3D Stereo Enhancement ON/OFF - 1 = on Mono output select - 0 = Mix, 1= Mic Mic select - 0 = Mic1, 1 = Mic2 DAC bypasses mixer and connects directly to Line Out ADC/DAC loopback mode 6.5.8. 3D Control (22h) Default: 0000h D15 D7 D14 D6 Reserved D13 D5 D12 Reserved D11 D3 DP3 D10 D2 DP2 D9 D1 Reserved D8 D0 D4 This register is used to control the 3D stereo enhancement function, IDT Surround 3D (SS3D), built into the AC'97 component. Note that register bits DP3-DP2 are used to control the separation ratios in the 3D control for LINE_OUT. SS3D provides for a wider soundstage extending beyond the normal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to 1 to enable SS3D functionality and for the bits in 22h to take effect. Table 22. 3D Control Registers DP3, DP2 00 01 10 11 LINE_OUT SEPARATION RATIO 0 (Off) 3 (Low) 4.5 (Med) 6 (High) The three separation ratios are implemented as shown in Table 22. The separation ratio defines a series of equations that determine the amount of depth difference (High, Medium, and Low) perceived during two-channel playback. The ratios provide for options to narrow or widen the soundstage. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 40 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.9. Audio Interrupt (24h) Default: 0000h D15 I4 D14 I3 D13 Reserved D12 D4 Reserved D11 I0 D10 D2 D9 Reserved D8 D0 D7 D6 D5 D3 D1 Bit(s) Reset R/W Value Name Description 0 = Interrupt is clear 1 = Interrupt is set Interrupt event is cleared by writing a 1 to this bit. The interrupt bit will change regardless of condition of interrupt enable (I0) status. An interrupt in the GPI in slot 12 in the AC-Link will follow this bit change when interrupt enable (I0) is unmasked. Interrupt Cause 0 = No Interrupt Caused 1 = Change in GPIO input status 15 0 RW I4 14 0 RO I3 These bits will reflect the general cause of the first interrupt event generated. It should be read after interrupt status has been confirmed as interrupting. The information should be used to scan possible interrupting events in proper pages. 13-12 0 RW Reserved Bits not used, should read back 0 Interrupt Enable 0 = Interrupt generation is masked. 1 = Interrupt generation is un-masked. The driver should not un-mask the interrupt unless ensured by the AC `97 controller that no conflict is possible with modem slot 12 - GPI functionality. Some AC'97 2.2 compliant controllers do not support audio CODEC interrupt infrastructure. In either case, S/W should poll the interrupt status after initiating a sense cycle and wait for Sense Cycle Max Delay to determine if an interrupting event has occurred. 11 0 RW I0 10:0 0 RO Reserved Bits not used, should read back 0 6.5.10. Powerdown Ctrl/Stat (26h) Default: 000Fh D15 EAPD D14 PR6 D13 PR5 D12 PR4 D11 PR3 D10 PR2 D9 PR1 D8 PR0 D7 D6 Reserved D5 D4 D3 REF D2 ANL D1 DAC D0 ADC IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 41 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO This read/write register is used to program power down states and monitor subsystem readiness. The EAPD external control is also supported through this register. Table 23. Powerdown Status Registers Bit EAPD REF ANL DAC ADC External Amplifier Power Down VREF's up to nominal level Analog mixers, etc. ready DAC section ready to playback data ADC section ready to playback data Function 6.5.10.1. Ready Status The lower half of this register is read only status, a 1 indicating that the subsection is ready. Ready is defined as the subsection's ability to perform in its nominal state. When this register is written, the bit values that come in on AC-Link will have no effect on read only bits 0-7. When the AC-Link "CODEC Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any are ready. When this register is written, the bit values that come in on AC-Link will have no effect on read only bits 0-7. 6.5.10.2. Powerdown Controls The STAC9750/9751 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). See the section "Low Power Modes" for more information. 6.5.10.3. External Amplifier Power Down Control The EAPD bit 15 of the Powerdown Control/Status Register (Index 26h) directly controls the output of the EAPD output (pin 45), and produces a logical 1 when this bit is set to logic high. This function is used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibility. 6.5.11. Extended Audio ID (28h) Default: 0605h D15 ID1 D14 ID0 D13 Reserved D12 D4 DSA0 D11 REV1 D10 REV0 D9 AMAP D8 LDAC D7 SDAC D6 CDAC D5 DSA1 D3 VRM D2 SPDIF D1 DRA D0 VRA IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 42 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO The Extended Audio ID register is a read-only register, except for bits D5:D4. ID1 and ID0 echo the configuration of the CODEC as defined by the programming of pins 45 and 46 externally. A returned 00 defines the CODEC as the primary CODEC, while any other code identifies the CODEC as one of three secondary CODEC possibilities. SDAC = 0 tells the controller that the STAC9750/9751 is a two-channel CODEC as defined by the Intel specification. The AMAP bit, D9, will return a 1 indicating that the CODEC supports the optional "AC'97 2.2 compliant AC-link slot to audio DAC mappings". The default condition assumes that 00 are loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 00 in the DSAx bits, the CODEC slot assignments are as per the AC'97 specification recommendations. If the DSAx bits do not contain 00, the slot assignments are as per the table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicating that the CODEC supports the optional variable sample rate conversion as defined by the AC'97 specification. Table 24. Extended Audio ID Bit 15:14 13:12 11:10 9 8 7 6 Name ID [1,0] Reserved Rev[1:0] AMAP LDAC SDAC CDAC Access Read only Read only Read only Read only Read only Read only Read only Reset Value variable 00 01 1 0 0 0 Function 00 = XTAL_OUT grounded (Note 1) CID1#, CID0# = XTAL_OUT crystal or floating Reserved Indicates CODEC is AC'97 Rev 2.2 compliant Multi-channel slot support (Always = 1) Low Frequency Effect, not supported (Always=0) Surround DAC, not supported (Always = 0) Center channel, not supported (Always = 0) DAC slot assignment If CID[1:0] = 00 then DSA[1:0] resets to 00 If CID[1:0] = 01 then DSA[1:0] resets to 01 If CID[1:0] = 10 then DSA[1:0] resets to 01 If CID[1:0] = 11 then DSA[1:0] resets to 10 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 5:4 DSA [1,0] Read/Write 00 3 2 1 0 VRM SPDIF DRA VRA Read only Read only Read only Read only 0 1 0 1 Variable Sample Rate Mic, not supported (Always = 0) 0 = SPDIF pulled high on reset, SPDIF disabled 1 = default, SPDIF enabled (Note 2) Double Rate Audio, not supported (Always = 0) Variable sample rates supported (Always = 1) 1. External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin 45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source in primary mode only. Secondary mode can either be through BIT CLK driven or 24 MHz clock driver with XTAL_OUT floating/shorted. 2. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not available. Pin 48: To Enable SPDIF, use an 1 K-10 K external pulldown. To Disable SPDIF, use an 1 K-10 K external pullup. Do NOT leave Pin 48 floating. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 43 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.12. Extended Audio Control/Status (2Ah) Default: 0400h D15 D7 Reserved D14 D6 D13 Reserved D12 D4 SPSA0 D11 D3 RSRVD D10 SPCV D9 Reserved D8 D0 VRA enable D5 SPSA1 D2 SPDIF D1 RSRVD 6.5.12.1. Variable Rate Sampling Enable The Extended Audio Status Control register also contains one active bit to enable or disable the Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA, bit D0, is 1, the variable sample rate control registers (2Ch and 32h) are active, and "on-demand" slot data required transfers are allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 KHz data rate. The STAC9750/9751 supports "on-demand" slot request flags. These flags are passed from the CODEC to the AC'97 controller in every audio input frame. Each time a slot request flag is set (active low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable "on-demand" data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz transfers and every audio frame will include an active slot request flag and data is transferred every frame. For variable sample rate output, the CODEC examines its sample rate control registers, the state of the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current audio input frame for active output slots, which will require data in the next audio output frame. For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN (CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz). 6.5.12.2. SPDIF The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the SPDIF functionality within the STAC9750/9751. If the SPDIF is set to a 1, then the function is enabled and when set to a 0 it is disabled. 6.5.12.3. SPCV (SPDIF Configuration Valid) The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When SPCV is a 0, it indicates the system configuration is invalid and valid if it is a 1. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 44 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.12.4. SPSA1, SPSA0 (SPDIF Slot Assignment) SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following details the slot assignment relationship between SPSA1 and SPSA0. Table 25. Slot assignment relationship between SPSA1 and SPSA0 SPSA[1,0] 00 01 10 11 Slot Assignment 3&4 7&8 6&9 10 & 11 Comments SPDIF source data slot assignment 2-channel CODEC primary default 4-channel CODEC primary default 6-channel CODEC primary default The STAC9750/9751 are AMAP compliant with the following table. Table 26. STAC9750/9751 AMAP compliant CODEC ID 00 01 10 11 Function 2-channel Primary w/SPDIF 2-channel Dock CODEC w/SPDIF +2-channel Surr w/ SPDIF +2-channel Cntr/LFE w/ SPDIF SPSA = 00 3&4 3&4 3&4 SPSA = 01 7 & 8* 7&8 7&8 SPSA = 10 6&9 6 & 9* 6 & 9* SPSA = 11 10 & 11 10 & 11 10 & 11 10 & 11* 3&4 7&8 6&9 Note: * is the default slot assignment 6.5.13. PCM DAC Rate Registers (2Ch and 32h) The internal sample rate for the DACs and ADCs are controlled by the value in these read/write registers that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported, that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample rates are supported for record and playback. Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h) will read back with BB80h (48 KHz). Table 27. Hardware Supported Sample Rates Sample Rate 8 KHz 11.025 KHz 16 KHz 22.05 KHz 32 KHz 44.1 KHz 48 KHz SR15-SR0 Value 1F40h 2B11h 3E80h 5622h 7D00h AC44h BB80h IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 45 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.14. PCM DAC Rate (2Ch) Default: BB80h D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0 6.5.15. PCM LR ADC Rate (32h) Default: BB80h D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 SR9 D8 SR8 D7 SR7 D6 SR6 D5 SR5 D4 SR4 D3 SR3 D2 SR2 D1 SR1 D0 SR0 6.5.16. SPDIF Control (3Ah) Default: 2A00h D15 #V D14 DRS D13 SPSR1 D12 SPSR2 D11 L D10 CC6 D9 CC5 D8 CC4 D7 CC3 D6 CC2 D5 CC1 D4 CC0 D3 PRE D2 COPY D1 #PCM/AUDIO D0 PRO Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or sub-frame in the V case). With exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit register 2 Ah is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission. The default is 2A00h which sets the SPDIF output sample rate at 48 KHz and the normal SPDIF expectations. Table 28. SPDIF Control Bit(s) Reset 15 14 0 0 Access Read & Write Read Only Name #V DRS Description (note 1-2) Validity bit is set indicating each sub-frame's samples are invalid. If #V is 0, then it indicates that each sub-frame was transmitted and received correctly by the interface. 1 = Double Rate SPDIF support (always = 0) 13:12 10 SPDIF Sample Rate. 00 44.1 KHz Rate Read & Write SPSR[1,0] 01 Reserved 10 48 KHz Rate (default) 11 32 KHz Rate Read & Write L Generation Level is defined by the IEC standard, or as appropriate. (Always = 1) 11 0 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 46 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Table 28. SPDIF Control (Continued) Bit(s) Reset 10:4 3 2 1 0 0 0 0 0 0 Access Read & Write Read & Write Read & Write Read & Write Read & Write Name CC[6, 0] PRE COPY /AUDIO PRO Description (note 1-2) Category Code is defined by the IEC standard or as appropriate by media. 0 = 0 sec Pre-emphasis 1 = Pre-emphasis is 50/15 sec 0 = Copyright not asserted 1 = Copyright is asserted 0 = PCM data 1 = Non-Audio or non-PCM format 0 = Consumer use of the channel 1 = Professional use of the channel 1. If pin 48 is held high at powerup, 28h D2 will be low indicating no SPDIF available and the register 3Ah will then read back 0000h. Pin 48: To Enable SPDIF, use an 1 K-10 K external pulldown. To Disable SPDIF, use an 1 K-10 K external pullup. Do NOT leave Pin 48 floating. 2. Bits D15, D13-D00 of this register cannot be written to without first setting Reg 2Ah bit D2 = 0 (SPDIF disabled) and Register 28h bit D2 = 1 (SPDIF available). 6.5.17. Extended Modem Status and Control Register (3Eh) Default: 0100h D15 D7 D14 D6 D13 D5 D12 Reserved D11 D3 D10 D2 D9 D1 D8 PRA D4 Reserved D0 GPIO Table 29. Extended Modem Status and Control Bit(s) 15:9 8 7:1 0 Access Read Only Read / Write Read Only Read Only Reset Value 0 1 0 0 Name Reserved PRA Reserved GPIO Description Bit not used, should read back 0 0 = GPIO powered up / enabled 1 = GPIO powered down / disabled Bit not used, should read back 0 0 = GPIO not ready (powered down) 1 = GPIO ready (powered up) 6.5.18. GPIO Pin Configuration Register (4Ch) Default: 0003h D15 D7 D14 D6 D13 D5 Reserved D12 Reserved D11 D3 D10 D2 D9 D1 GC1 (GPIO1) D8 D0 GC0 (GPIO0) D4 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 47 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Table 30. GPIO Pin Configuration Register Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 1 1 Name Reserved GC1 GC0 Description Bit not used, should read back 0 0 = GPIO1 configured as output 1 = GPIO1 configured as input 0 = GPIO0 configured as output 1 = GPIO0 configured as input 6.5.19. GPIO Pin Polarity/Type Register (4Eh) Default: FFFFh D15 D7 D14 D6 D13 D5 Reserved D12 Reserved D11 D3 D10 D2 D9 D1 GP1 (GPIO1) D8 D0 GP0 (GPIO0) D4 Table 31. GPIO Pin Polarity/Type Register Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 1 1 Name Description 0 = GPIO1 Input Polarity Inverted, CMOS output drive. 1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive. 0 = GPIO0 Input Polarity Inverted, CMOS output drive. 1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive. Reserved Bit not used, should read back 0 GP1 GP0 6.5.20. GPIO Pin Sticky Register (50h) Default: 0000h D15 D7 D14 D6 D13 D5 Reserved D12 Reserved D11 D3 D10 D2 D9 D1 GS1 (GPIO1) D8 D0 GS0 (GPIO0) D4 Table 32. GPIO Pin Sticky Register Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 0 0 Name Reserved GS1 GS0 Description Bit not used, should read back 0 0 = GPIO1 Non Sticky configuration. 1 = GPIO1 Sticky configuration. 0 = GPIO0 Non Sticky configuration. 1 = GPIO0 Sticky configuration. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 48 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.21. GPIO Pin Mask Register (52h) Default: 0000h D15 D7 D14 D6 D13 D5 Reserved D12 Reserved D11 D3 D10 D2 D9 D1 GW1 (GPIO1) D8 D0 GW0 (GPIO0) D4 Table 33. GPIO Pin Mask Register Bit(s) 15:2 1 0 Access Read Only Read / Write Read / Write Reset Value 0 0 0 Name Reserved GW1 GW0 Description Bit not used, should read back 0 0 = GPIO1 interrupt not passed to GPIO_INT slot 12. 1 = GPIO1 interrupt is passed to GPIO_INT slot 12. 0 = GPIO0 interrupt not passed to GPIO_INT slot 12. 1 = GPIO0 interrupt is passed to GPIO_INT slot 12. 6.5.22. GPIO Pin Status Register (54h) Default: 0000h D15 D7 D14 D6 D13 D5 Reserved D12 Reserved D11 D3 D10 D2 D9 D1 GI1 (GPIO1) D8 D0 GI0 (GPIO0) D4 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 49 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Table 34. GPIO Pin Status Register Bit(s) 15:2 Access Read Only Reset Value 0 Name Description When GPIO1 is configured as output and Register 74h bit[0] = 0 (default), the value of this register will be placed on the GPIO1 pad. When GPIO1 is configured as output and Register 74h bit[0] =1, the GPIO1 pad will get its value from slot12. Reserved Bit not used, should read back 0 1 Read / Write x GI1 When GPIO1 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. When GPIO1 is configured as input this register reflects the value on the GPIO1 pad after interpretation of the polarity and sticky configurations. When GPIO0 is configured as output and Register 74h bit[0] = 0 (default), the value of this register will be placed on the GPIO0 pad. When GPIO0 is configured as output and Register 74h bit[0] =1, the GPIO0 pad will get its value from slot12. 0 Read / Write x GI0 When GPIO0 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. When GPIO0 is configured as input this register reflects the value on the GPIO0 pad after interpretation of the polarity and sticky configurations. 6.5.23. Digital Audio Control (6Ah) Default: 0000h D15 D7 D14 D6 D13 D5 Reserved D12 Reserved D11 D3 D10 D2 D9 D1 DO1 D8 D0 DO0 D4 Table 35. Digital Audio Control Register Bit(s) 15:2 1 0 Reset 0 0 0 Name Reserved DO1 DO0 Description Bits not used, should read back 0 SPDIF Digital Output Source Selection: DO1 = 0; PCM data from the AC-Link to SPDIF DO1 = 1; ADC record data to SPDIF Always reads zero This read/write register is used to program the digital mixer input status. In the default state, the PCM DAC path is enabled and the ADC record inputs are disabled. The DO1 and DO0 bits control the input source for the PCM to digital output converters. The table describes the available options. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 50 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.24. Revision Code (6Ch) Default: 00xxh D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 The device Revision Code register (index 6Ch) contains a software readable revision-specific code used to identify performance, architectural, or software differences between various device revisions. Bits 7:0 of the Revision Code register are user readable; bits 15:8 are not used at this time and will return zeros when read. This value can be used by the audio driver, or miniport driver in the case of WIN98(R) WDM approaches, to adjust software functionality to match the feature-set of the STAC9750/9751. This will allow the software driver to identify any required operational differences between the existing STAC9750/9751 and future versions. 6.5.25. Analog Special (6Eh) Default: 0000h D15 D7 RSVD D14 Reserved D13 D5 ADCSLT1 D12 AC97 ALL MIX D11 D3 Reserved D10 Reserved D9 D1 SPLYOVR EN D8 D0 SPLYOVR VAL D6 MUTE FIX DISABLE D4 ADCSLT0 D2 20/30 SEL The Analog Special register has several bits used to control various functions specific to the STAC9750/9751. 6.5.25.1. ALL MIX The AC'97 ALL_MIX, bit D12 of register 6Eh, controls the record source when the Stereo Mix option is selected for recording. If the AC'97 mode is default logic 1, the "Stereo Mix Record" option will include the sum of the analog sources with or without 3D enhancement, and the main PCM DAC output. If the "ALL Analog Record" option is selected, the Stereo Mix Record option will include the sum of the analog sources only, with or without 3D enhancement. The "AC'97 mode" is useful for recording all sound sources. The "ALL Analog Record" mode is useful in conjunction with the POP BYPASS mode for recording all analog sources, which are often further processed and combined with other PCM data to be output directly to the DAC outputs which are configured in POP_BYPASS mode using the General Purpose register (index 20h). IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 51 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.25.2. ADC Data on AC LINK Bits D5-D4 select slots for ADC data on ACLINK. Table 36. ADC data on AC LINK Value 00 01 10 11 Function left slot 3, right slot 4 left slot 7, right slot 8 left slot 6, right slot 9 left slot 10, right slot 11 6.5.25.3. MuteFix Disable Bit D6 controls the enable and disable of the MuteFix functions. * * 0 = MUTE FIX Enabled 1 = MUTE FIX Disabled When this bit is zero, and either channel is set to -46.5dB attenuation (1Fh), then that channel is fully muted. When this bit is one, then operation is per AC'97 specification. This bit is reserved in revisions prior to CC1. 6.5.25.4. Mic Boost Select The Mic boost value can be selected with bit D2, which in enabled by Register 0Eh, bit D6. Writing a zero to bit D2 will provide 20dB of Mic Boost. Writing a one will provide 30dB of Mic Boost. Table 37. Mic Boost Select Value 0 1 Function 20dB 30dB 6.5.25.5. Supply Override Select The Supply Override bit, D1, allows override of the supply detect. Writing a zero disables the override on supply detect. Writing a one, overrides supply detect with bit D0. Bit D0 provides the supply override value. A zero forces 3.3 V analog operation and one forces 5 V analog operation. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 52 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.25.6. 72h Enable (70h) Default: 0000h D15 EN15 D14 EN14 D13 EN13 D12 EN12 D11 EN11 D10 EN10 D9 EN9 D8 EN8 D7 EN7 D6 EN6 D5 EN5 D4 EN4 D3 EN3 D2 EN2 D1 EN1 D0 EN0 6.5.25.7. Analog Current Adjust (72h) Default: 0000h D15 D7 INT APOP D14 D6 D13 D5 Reserved D12 Reserved D11 D3 D10 D2 IBIAS1 D9 D1 IBIAS0 D8 D0 RSVD D4 The Analog Current Adjust register (index 72h) is a locked register and can only be properly written and read from when ABBAh has been written into register 70h. The IBIASx bits allow the analog current to be adjusted with minimal reduction in performance. A lower analog current setting is NOT recommended when a 5V analog supply is used. A lower setting for 3.3V supplies is recommended for notebook computers to reduce power consumption to its lowest level. Table 38. Analog Current Adjust IBIAS1 0 0 1 1 IBIAS0 0 1 0 1 Analog Current Normal Current 80% of nominal Analog Current 120% of nominal Analog Current 140% of nominal Analog Current 6.5.25.8. Internal Power-On/Off Anti-Pop Circuit The STAC9750/9751 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the CODEC is powered on and off. This function is accomplished by delaying the charge/discharge of the VREF capacitor (Pin 27). CVREF value of 1 F will cause a turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the CODEC outputs are enabled. The delay can be extended to 30 seconds if a value of CVREF value of 10 F is used. The CODEC outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. The INT_APOP bit D7 of register 72h allows this delay circuit to be bypassed for rapid production testing. Any external component anti-pop circuit is unaffected by the internal circuit. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 53 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.26. GPIO Access Register (74h) Default: 0800h D15 EAPD D14 Reserved D13 GPIO1 D12 GPIO0 D11 EAPD_OEN D10 Reserved D9 D1 D8 D0 GPIO1_OEN GPIO0_OEN D7 D6 D5 D4 Reserved D3 D2 Table 39. GPIO Access Registers (74h) Bit(s) 15 14 13 12 11 10 9 8 7:0 Reset Value 0 0 0 0 1 0 0 0 0 Name EAPD Reserved GPIO1 GPIO0 EAPD_OEN Reserved GPIO1_OEN GPIO0_OEN Reserved Description EAPD data output on EAPD when bit D11 = 1 EAPD data input from pin when bit D11 = 0 Reserved GPIO1 data output on GPIO1 when bit D9 = 1 GPIO1 data input from pin when bit D9 = 0 GPIO0 data output on GPIO0 when bit D8 = 1 GPIO0 data input from pin when bit D8 = 0 0 = EAPD data out disabled 1 = EAPD data output enabled Reserved 0 = GPIO1 data out disabled 1 = GPIO1 data output enabled 0 = GPIO0 data out disabled 1 = GPIO0 data output enabled Reserved The GPIO Access Register requires that the output enable bits (D11, D9 and D8) be used in conjunction with the data source selection (input or output) for the EAPD, GPIO0 and GPIO1 (pins 47, 43 and 44 respectively). For example, to use GPIO1 as an output, set D9 = 1 to enable the output, and use D13 to write the output value desired. To use GPIO1 as an input, set D9 = 0 to disable the output, and use D13 to read the input value. 6.5.27. High Pass Filter Bypass (Index 76h and 78h) The High Pass Filter Bypass register (index 78h) is a locked register and can only be properly written and read from when ABBAh has been written into register 76h. Bit D0 controls the High Pass Filter Bypass. Default is zero which provides for normal operation where the high pass filter is active. Writing a one, will disable, or bypass the ADC high pass filter. 6.5.27.1. 78h Enable (76h) Default: 0000h D15 EN15 D14 EN14 D13 EN13 D12 EN12 D11 EN11 D10 EN10 D9 EN9 D8 EN8 D7 EN7 D6 EN6 D5 EN5 D4 EN4 D3 EN3 D2 EN2 D1 EN1 D0 EN0 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 54 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 6.5.27.2. ADC High Pass FIlter Bypass(78h) Default: 0000h D15 D7 D14 D6 D13 D5 D12 D4 Reserved D11 Reserved D10 D2 D9 D1 D8 D0 ADC HPF BYP D3 6.5.28. Vendor ID1 and ID2 (Index 7Ch and 7Eh) These two registers contain four 8-bit ID codes. The first three codes have been assigned by Microsoft using their Plug and Play Vendor ID methodology. The fourth code is an IDT assigned code identifying the STAC9750/9751. The ID1 register (index 7Ch) contains the value 8384h, which is the first (83h) and second (84h) characters of the Microsoft ID code. The ID2 register (index 7Eh) contains the value 7650h, which is the third (76h) of the Microsoft ID code, and 50h which is the STAC9750/9751 ID code. Note: The lower half of the Vendor ID2 register (index 7Eh) currently contains the value xxh identifying the STAC9750/9751. This value can be used by the audio driver, or miniport driver in the case of WIN98(R), to adjust software functionality to match the feature-set of the STAC9750/9751. This portion of the register will likely contain different values if the software profile of the STAC9750/9751 changes, as in the case of silicon level device modifications. This will allow the software driver to identify any required operational differences between the existing STAC9750/9751 and any future versions. 6.5.28.1. Vendor ID1 (7Ch) Default: 8384h D15 1 D14 0 D13 0 D12 0 D11 0 D10 0 D9 1 D8 1 D7 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 0 6.5.28.2. Vendor ID2 76xx (7Eh) Default: 7650h D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 1 D8 0 D7 0 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 55 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 7. LOW POWER MODES The STAC9750/9751 is capable of operating at reduced power when no activity is required. The state of power-down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The power down options are listed in Table 40. The first three bits, PR0..PR2, can be used individually or in combination with each other, and control power distribution to the ADCs, DACs and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR0, PR1, and PR2. PR3 essentially removes power from all analog sections of the CODEC, and is generally only asserted when the CODEC will not be needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 must be "set" before PR4. PR5 disables the internal CODEC clock and requires an external cold reset for recovery. PR6 disables the headphone driver amplifier for additional analog power saving. Table 40. Low Power Modes GRP Bits PR0 PR1 PR2 PR3 PR4 PR5 PR6 PCM out DACs Powerdown Analog Mixer power down (VREF still on) Analog Mixer power down (VREF off) Digital Interface (AC-Link) power down (external clock off) Internal Clock disable Powerdown HEADPHONE_OUT Function PCM in ADCs & Input Mux Powerdown The Figure 19 illustrates one example procedure to do a complete power down of STAC9750/9751. From normal operation, sequential writes to the Powerdown Register are performed to power down STAC9750/9751 a piece at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9750/9751 can also be woken up with a cold reset. A cold reset will reset all of the registers to their default states. When a section is powered back on, the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it. Figure 19. Example of STAC9750/9751 Powerdown/Powerup Flow PR0=1 PR1=1 PR2=1 PR4=1 Normal ADCs off PR0 DACs off PR1 Analog off PR2 or PR3 Digital I/F off PR4 Shut off AC-Link PR0=0 & ADC=1 PR1=0 & DAC=1 PR2=0 & ANL=1 Warm Reset Default Ready =1 Cold Reset IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 56 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Figure 20 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through STAC9750/9751 to the speakers, while most of the system in low power mode. The procedure for this follows the previous except that the analog mixer is never shut down. Figure 20. STAC9750/9751 Powerdown/Powerup Flow With Analog Still Active PR0=1 PR1=1 PR4=1 Normal ADCs off PR0 DACs off PR1 Digital I/F off PR4 Shut off AC-Link PR0=0 & ADC=1 PR1=0 & DAC=1 Warm Reset IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 57 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 8. MULTIPLE CODEC SUPPORT The STAC9750/9751 provides support for the multi-CODEC option according to the Intel AC'97, rev 2.2 specification. By definition there can be only one Primary CODEC (CODEC ID 00) and up to three Secondary CODECs (CODEC IDs 01, 10, and 11). The CODEC ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers. 8.1. Primary/Secondary CODEC Selection In a multi-CODEC environment the CODEC ID is provided by external programming of pins 45 and 46 (CID0 and CID1). The CID pin electrical function is logically inverted from the CODEC ID designation. The corresponding pin state and its associated CODEC ID are listed in the "CODEC ID Selection" table. Also see slot assignment discussion, "Multi-Channel Programming Register (Index 74)". Table 41. CODEC ID Selection CID1 State DVdd or floating DVdd or floating 0V 0V CID0 State DVdd or floating 0V DVdd or floating 0V CODEC ID 00 01 10 11 CODEC Status Primary Secondary Secondary Secondary 8.1.1. Primary CODEC Operation As a Primary device the STAC9750/9751 is completely compatible with existing AC'97 definitions and extensions. Primary CODEC registers are accessed exactly as defined in the AC'97 Component Specification and AC'97 Extensions. The STAC9750/9751 operates as Primary by default, and the external ID pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for primary operation. When used as the Primary CODEC, the STAC9750/9751 generates the master AC-Link BIT_CLK for both the AC'97 Digital Controller and any Secondary CODECs. The STAC9750/9751 can support up to four loads of 10 K and 50 pF on the BIT_CLK line. This is to ensure that implementations of up to four CODECs will not load down the clock output. 8.1.2. Secondary CODEC Operation When the STAC9750/9751 is configured as a Secondary device the BIT_CLK pin is configured as an input at power up. Using the BIT_CLK provided by the Primary CODEC insures that everything on the AC-Link will be synchronous. As a Secondary device it can be defined as CODEC ID 01, 10 or 11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s). IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 58 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 8.2. Secondary CODEC Register Access Definitions The AC'97 Digital Controller can independently access Primary and Secondary CODEC registers by using a 2-bit CODEC ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary CODEC access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0). As a Secondary CODEC, the STAC9750/9751 will disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits when it sees a 2-bit CODEC ID value (Slot 0, bits 1 and 0) that matches its configuration. In a sense the Secondary CODEC ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator. Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the Secondary CODEC ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the Secondary CODEC ID bits are set. This method is designed to be backward compatible with existing AC'97 controllers and CODECs. There is no change to output Slot 1 or 2 definitions. Table 42. Secondary CODEC Register Access Slot 0 Bit Definitions Output Tag Slot (16-bits) Bit 15 14 13 12-3 2 Frame Valid Slot 1 Valid Command Address bit ( Primary CODEC only) Slot 2 Valid Command Data bit ( Primary CODEC only) Slot 3-12 Valid bits as defined by AC'97 Reserved (Set to 0) Description Note: 1-0 2-bit CODEC ID field (00 Reserved for Primary; 01, 10, 11 indicate Secondary) New definitions for Secondary CODEC Register Access IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 59 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 9. TESTABILITY The STAC9750/9751 has two test modes. One is for ATE in-circuit test and the other is restricted for IDT's internal use. STAC9750/9751 enters the ATE in-circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC from the AC-Link when another CODEC is to be used as the primary. This case will never occur during standard operating conditions. Once either of the two test modes have been entered, the STAC9750/9751 must be issued another RESET# with all AC-link signals held low to return to the normal operating mode. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 60 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 10. PIN DESCRIPTION Figure 21. STAC9750/9751 Pin Description Drawing LINE_OUT_R LINE_OUT_L NC NC CAP2 NC AFILT2 AFILT1 VREFout VREF AVss1 AVdd1 MONO_OUT AVdd2 HP_OUT_L HP_COMM HP_OUT_R AVss2 GPIO0 GPIO1 CID0 CID1 EAPD SPDIF 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 48-Pin LQFP 24 23 22 21 20 19 18 17 16 15 14 13 LINE_IN_R LINE_IN_L MIC2 MIC1 CD_R CD_GND CD_L VIDEO_R VIDEO_L AUX_R AUX_L PHONE Pin 48: To Enable SPDIF, use an 1 K-10 K external pulldown. To Disable SPDIF, use an 1 K-10 K external pullup. Do NOT leave Pin 48 floating. The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS DVdd1 1 XTL_IN 2 XTL_OUT 3 DVss1 4 SDATA_OUT 5 BIT_CLK 6 DVss2 7 SDATA_IN 8 DVdd2 9 SYNC 10 RESET# 11 PC_BEEP 12 61 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 10.1. Digital I/O These signals connect the STAC9750/9751 to its AC'97 controller counterpart, an external crystal, multi-CODEC selection and external audio amplifier. Table 43. Digital Connection Signals Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA__IN SYNC RESET# NC NC NC GPIO0 GPIO1 CID0 CID1 EAPD Pin # Type 2 3 5 6 8 10 11 31 33 34 43 44 45 46 47 I I/O I I/O O I I I/O I/O I/O I/O I/O I I I/O Description 24.576 MHz Crystal or External Clock Source 24.576 MHz Crystal or ground if external clock source connected to XTAL_IN Serial, time division multiplexed, AC'97 input stream 12.288 MHz serial data clock Serial, time division multiplexed, AC'97 output stream 48 KHz fixed rate sample sync AC'97 Master H/W Reset No Connect No Connect No Connect General Purpose I/O General Purpose I/O Multi-CODEC ID select - bit 0 Multi-CODEC ID select - bit 1 External Amplifier Power Down SPDIF digital output Pin 48: - To Enable SPDIF, use an 1 K-10 K external pulldown. To Disable SPDIF, use an 1 K-10 K external pullup. Do NOT leave Pin 48 floating. SPDIF 48 O IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 62 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 10.2. Analog I/O These signals connect the STAC9750/9751 to analog sources and sinks, including microphones and speakers. Table 44. Analog Connection Signals Pin Name PC-BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_COMM HP_OUT_R Pin # 12 13 14 15 16 17 18 19 20 21 22 23 24 35 36 37 39 40 41 Type I* I* I* I* I* I* I* I* I* I* I* I* I* O O O O O O PC Speaker beep pass-through Description From telephony subsystem speakerphone (or DLP - Down Line Phone) Aux Left Channel Aux Right Channel Video Audio Left Channel Video Audio Right Channel CD Audio Left Channel CD Audio analog signal return CD Audio Right Channel Desktop Microphone Input Second Microphone Input Line In Left Channel Line In Right Channel Line Out Left Channel Line Out Right Channel To telephony subsystem speakerphone (or DLP - Down Line Phone) Headphone Out Left Channel Headphone Ground Return Headphone Out Right Channel * any unused input pins should be tied together through a capacitor (0.1 F suggested) to ground, except the MIC inputs which should have their own capacitor to ground if not used. CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5 V. The name of the pin in the AC'97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect The IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 63 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 10.3. Filter/References/GPIO These signals are connected to resistors, capacitors, specific voltages, or provide General Purpose I/O. Table 45. Filtering and Voltage References Signal Name VREF VREFOUT AFILT1 AFILT2 CAP2 Pin Number 27 28 29 30 32 Type O O O O O Description Analog ground (0.45 * Vdd, at 5 V; 0.41 * Vdd at 3 V) Reference Voltage out 5 mA drive (intended for MIC bias) (~Vdd/2) Anti-Aliasing Filter Cap - ADC left channel Anti-Aliasing Filter Cap - ADC right channel ADC reference Cap 10.4. Power and Ground Signals Table 46. Power and Ground Signals Pin Name AVdd1 AVdd2 AVss1 AVss2 DVdd1 DVdd2 DVss1 DVss2 Pin # 25 38 26 42 1 9 4 7 Type I I I I I I I I Analog Vdd = 5.0 V or 3.3 V Description Analog Vdd = 5.0 V or 3.3 V (headphone power source) Analog Gnd Analog Gnd Digital Vdd = 3.3 V Digital Vdd = 3.3 V Digital Gnd Digital Gnd IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 64 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 11. ORDERING INFORMATION Ordering Information Part Number STAC9750XXTAEyyX STAC9751XXTAEyyX Package 48-pin RoHS LQFP 7mm x 7mm x 1.4mm 48-pin RoHS LQFP 7mm x 7mm x 1.4mm Temp Range 0 C to +70 C 0 C to +70 C Supply Range DVdd = 3.3V, AVdd = 5.0V DVdd = 3.3V, AVdd = 3.3V NOTE: When ordering these parts the "yy" will be replaced with the CODEC revision. Add an "R" to the end of any of these part numbers for delivery on Tape and Reel. The minimum order quantity for Tape and Reel is 2,000 units. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 65 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 12. PACKAGE DRAWINGS 12.1. 48-Pin LQFP Figure 22. Package Drawing - 48-pin LQFP A2 D D1 b A A1 Key A A1 A2 D D1 E E1 L e c b c LQFP Dimensions in mm Min. Nom. Max. 1.40 0.05 1.35 8.80 6.90 8.80 6.90 0.45 0.09 0.17 1.50 0.10 1.40 9.00 7.00 9.00 7.00 0.60 0.50 0.22 0.20 0.27 1.60 0.15 1.45 9.20 7.10 9.20 7.10 0.75 E1 48 pin LQFP e Pin 1 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS E 66 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 13. SOLDER REFLOW PROFILE 13.1. Standard Reflow Profile Data Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds. FROM: IPC / JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices" (www.jedec.org/download). Profile Feature Average Ramp-Up Rate (Tsmax - Tp) Preheat Time maintained above Temperature Min (Tsmin) Temperature Max (Tsmax) Time (tsmin - tsmax) Temperature (TL) Time (tL) 3 C / second max 150 oC 200 oC 60 - 180 seconds 217 oC 60 - 150 seconds See "Package Classification Reflow Temperatures" on page 68. 20 - 40 seconds 6 oC / second max 8 minutes max o Pb Free Assembly Peak / Classification Temperature (Tp) Time within 5 oC of actual Peak Temperature (tp) Ramp-Down rate Time 25 oC to Peak Temperature Note: All temperatures refer to topside of the package, measured on the package body surface. Figure 23. Reflow Profile IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 67 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 13.2. Pb Free Process - Package Classification Reflow Temperatures Package Type LQFP 48-pin MSL 3 Reflow Temperature 260 oC* IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 68 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 14. APPENDIX A: SPLIT INDEPENDENT POWER SUPPLY OPERATION In PC applications, one power supply input to the STAC9750/9751 may be derived from a supply regulator (as shown in Figure 24) and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper on-chip partitioning of the analog and digital circuitry, some manufacturer's CODECs would be subject to on-chip SCR type latch-up. IDT's STAC9750/9751 specifically allows power-up sequencing delays between the analog (AVddx) and digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with no adverse effects to the CODEC. The IC is designed with independent analog and digital circuitry that prevents on-chip SCR type latch-up. However, the STAC9750/9751 is not designed to operate for extended periods with only the analog supply active. Note: Pin 48: To Enable SPDIF, use a 1 K-10 K external pulldown. To Disable SPDIF, use a 1 K-10 K external pullup. Do NOT leave Pin 48 floating. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 69 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Figure 24. STAC9750/9751 Split Independent Power Supply Operation Typical Connection Diagram 3.3V or 5V 5% *Suggested 3.3V 5% 0.1 F 1 F 0.1 F 0.1 F 10 F 0.1 F 25 AVdd1 38 AVdd2 1 DVdd1 9 27 pF DVdd2 XTL_IN 2 24.576 MHz 12 PC_BEEP 13 PHONE SDATA_OUT 14 AUX_L 15 AUX_R 16 VIDEO_L RESET# 17 VIDEO_R 18 CD_L 19 CD_GND 20 CD_R VREF 21 MIC1 22 MIC2 23 LINE_IN_L 24 LINE_IN_R *OPTIONAL 32 0.1 F 1 F* GPIO0 LINE_OUT_L 820 pF 29 AFILT1 LINE_OUT_R MONO_OUT AFILT2 HP_OUT_L AVss1 26 AVss2 42 DVss1 4 DVss2 7 HP_OUT_R 39 41 CAP2 GPIO1 HP_COMM NC NC NC SPDIF 31 33 34 48 40 44 43 35 36 37 VREFOUT 28 27 CID1 EAPD BIT_CLK SDATA_IN SYNC 5 6 8 10 11 45 46 47 XTL_OUT 3 27 pF 22 EMI Filter 27 pF OPTIONAL STAC9750 CID0 *OPTIONAL 0.1 F 1 F* 820 pF 30 *Terminate ground plane as close to codec as possible Analog Ground Digital Ground IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 70 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 15. APPENDIX B: PROGRAMMING REGISTERS Reg # 00h Name Reset HP_OUT Mixer Volume D15 RSRVD Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute Reserved Reserved Reserved Reserved Reserved Reserved Mute POP BYP RSRVD Reserved 3D GL3 Reserved GL4 GL4 GL4 GL4 GL4 GL3 GL3 GL3 GL3 GL3 GL2 GL2 GL2 GL2 GL2 SL2 GL2 D14 SE4 D13 SE3 D12 SE2 ML4 HPL4 D11 SE1 ML3 HPL3 D10 SE0 ML2 HPL2 Reserved Reserved Reserved Reserved GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX Reserved I4 EAPD ID1 I3 PR6 ID0 PR5 Reserved PR4 Reserved Reserved SR15 SR15 #V SR14 SR14 SR13 SR13 SR12 SR12 SPSR2 Reserved Reserved Reserved Reserved Reserved Reserved Mute Reserved GL4 GL3 GL2 GL1 Reserved 0 0 Reserved EN15 EN14 EN13 0 0 AC97 ALL MIX EN12 EN11 Reserved EAPD EN15 RSVD GPIO1 EN14 EN13 GPIO0 EN12 EAPD_OEN Reserved GPIO1_OEN GPIO0_OEN EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN10 0 0 0 Reserved EN9 EN8 INT EN7 APOP 0 0 0 0 0 0 0 GL0 Reserved GR4 GR3 GR2 SR11 SR11 L I0 PR3 REV1 (0) PR2 REV0 (1) SPCV SR10 SR10 CC6 SR9 SR9 CC5 PR1 AMAP PR0 LDAC RSRVD SR8 SR8 CC4 PRA SR7 SR7 CC3 SR6 SR6 CC2 SDAC Reserved Reserved CDAC DSA1 SPSA1 SR5 SR5 CC1 DSA0 REF ANL DAC DRA ADC VRA GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS LPBK boosted RSRVD Reserved Reserved Reserved Reserved Reserved Reserved Reserved GR3 Reserved DP3 DP2 Reserved D9 ID9 ML1 HPL1 D8 ID8 ML0 HPL0 D7 ID7 Reserved Reserved D6 ID6 D5 ID5 MR5 HPR5 MM5 D4 ID4 MR4 HPR4 MM4 PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 D3 ID3 MR3 HPR3 MM3 PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 D2 ID2 MR2 HPR2 MM2 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 D1 ID1 MR1 HPR1 MM1 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 D0 ID0 MR0 HPR0 MM0 Default 6990h 8000h 8000h 8000h 02h Master Volume 04h RSRVD ML5 RSRVD HPL5 Master Volume 06h Mono 0Ah PC_BEEP Volume Mic Volume CD Volume Video Volume AUX Volume PCM Out Volume Record Gain General Purpose 3D Control Powerdown Ctrl/Stat Extended Audio ID RSRVD 0000h GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h 000Fh 0605h 0Ch Phone Volume 0Eh 12h 14h 16h 18h 10h Line In Volume 1Ah Record Select 1Ch 20h 22h 24h Audio Interrupt 26h 28h RSVD SPDIF Extended 2Ah Audio Control/ Status 2Ch 32h PCM DAC Rate PCM LR ADC Rate SPSA0 RSRVD SPDIF RSRVD SR4 SR4 CC0 SR3 SR3 PRE SR2 SR2 COPY SR1 SR1 #PCM/ AUDIO VRA 0400h enable SR0 SR0 PRO GPIO BB80h BB80h 2A00h 0100h 3Ah SPDIF Control 3Eh 4Ch 4Eh 50h 52h 54h 60h 6Ah Extended Modem Status GPIO Pin Config GPIO Pin Polarity/Type GPIO Pin Sticky GPIO Pin Mask GPIO Pin Status Z_DATA Volume Digital Audio Control DRS SPSR1 Reserved GC1 GC0 0300h (GPIO1) (GPIO0) GP1 GP0 FFFFh (GPIO1) (GPIO0) GS1 GS0 0000h (GPIO1) (GPIO0) GW1 GW0 0000h (GPIO1) (GPIO0) GI1 GI0 0000h (GPIO1) (GPIO0) GR1 DO1 0 SPLY OVR EN EN1 GR0 DO0 0 SPLY OVR VAL EN0 RSVD 8808h 0000h 00xxh 1000h 0000h 0000h 0000h EN3 EN2 EN1 EN0 ADC HPF BYP 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0000h 0000h 8384h 7650h 6Ch Revision Code 6Eh Analog Special 70h 72h 72h Enable Analog Current Adjust 78h Enable High Pass Filter Bypass Vendor ID1 Vendor ID2 9750 MUTE MIC FIX ADCslot1 ADCslot0 RSVD GAIN DISBLE VALUE EN6 EN5 EN4 EN3 EN2 Reserved Reserved EN4 IBIAS<1:0> 74h* GPIO Access 76h 78h 7Ch 7Eh RSESERVED 1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 0 Note: All registers not shown, and those labeled "Reserved", can be written to but are "Don't Care" on read back. Note: PC_BEEP defaults to 0000h, mute off. IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 71 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO 16. REVISION HISTORY Revision Date Description of Change Corrected error on page 26: Slot 1 Status Address Port, bit D2 is a SLot Request not Reserved as stated in rev 5.1 Added CD_GND elaboration note on connection diagram, pin list and pin out diagrams: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about 2.5V. The name of the pin in the AC97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect. Corrected Note 4 in performance characteristics, was missing the text "Ratio of Full Scale signal to THD+N output with -3dB signal, measured "A weighted" over a". Complete note now reads "Ratio of Full Scale signal to THD+N output with -3dB signal, measured "A weighted" over a 20 Hz to a 20 KHz bandwidth. 48 KHz Sample Frequency". Added updated 48-pin package drawing. Added reflow profile information. Revised reflow profile information Revised TQFP to say LQFP. Updated with new logo template Added Part order information for RoHS package, with EOL information to Pb-bearing Removed references to older revisions (CA3) and their relationship to CC1, as CA3 is EOL and CC1 is the only production revision. Initial release in IDT format. 5.2 October 2003 5.3 June 2004 5.4 5.5 5.6 January 2005 February 2005 March 2005 5.7 December 2005 5.8 30 October 2006 IDTTM VALUE-LINE TWO-CHANNEL AC'97 CODECS 72 STAC9750/9751 V 5.8 103106 STAC9750/9751 VALUE-LINE TWO-CHANNEL AC'97 CODECS PC AUDIO Innovate with IDT audio for high fidelity. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support HA.CM@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. |
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